74SSTUA32866BFG8 Datasheet 74SSTUA32866BFG8, 74SSTUA32866BFG | P10-P12

COMMERCIAL TEMPERATURE RANGE

IDT74SSTUA32866

1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST

TERMINAL FUNCTIONS (ALL PINS)

Terminal Electrical

Name Characteristics Description

GND Ground Input Ground

VDD 1.8V nominal Power Supply Voltage

VREF 0.9V nominal Input Reference Voltage

CL K Differential Input Positive Master Clock Input

CLK Differential Input Negative Master Clock Input

Cx LVCMOS Input Configuration Control Inputs

RESET LVCMOS Input Asynchronous Reset Input. Resets registers and disables VREF data and clock differential-input receivers.

CSR, DCS SSTL_18 Input Chip Select Inputs. Disables outputs Dx switching when both inputs are HIGH.

D x SSTL_18 Input Data Input. Clocked in on the crossing of the rising edge of CLK and the falling edge of CLK.

DODT SSTL_18 Input The outputs of this register bit will not be suspended by the DCS and CSR controls

DCKE SSTL_18 Input The outputs of this register bit will not be suspended by the DCS and CSR controls

Q x 1.8V CMOS Data Outputs that are suspended by the DCS and CSR controls

QCSx 1.8V CMOS Data Output that will not be suspended by the DCS and CSR controls

QODTx 1.8V CMOS Data Output that will not be suspended by the DCS and CSR controls

QCKEx 1.8V CMOS Data Output that will not be suspended by the DCS and CSR controls

PAR_IN SSTL_18 Input Parity Input. Clocked on the rising edge of CLK one cycle after corresponding data input.

QERR Open Drain Output Output Error bit, generated one cycle after the corresponding data output

PPO 1.8V CMOS Partial Parity Output. Indicates ODD parity of Data Inputs and Parity In.

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Description Max. Unit

VDD Supply Voltage Range –0.5 to 2.5 V

(2,3)

Input Voltage Range –0.5 to 2.5 V

(2,3)

Output Voltage Range –0.5 to VDD +0.5 V

IK Input Clamp Current VI < 0 ±50 mA

VI > VDD

IOK Output Clamp Current VO < 0 ±50 mA

VO > VDD

IO Continuous Output Current, ±50 mA

VO = 0 to VDD

VDD Continuous Current through each ±100 mA

VDD or GND

STG Storage Temperature Range –65 to +150 ° C

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. The input and output negative voltage ratings may be exceeded if the ratings of the

I/P and O/P clamp current are observed.

3. This value is limited to 2.5V maximum.

MODE SELECT

C0 C1 Device Mode

0 0 1:1 25-bit to 25-bit

0 1 1:2 14-bit to 28-bit, Front (Type A)

1 0 Reserved

1 1 1:2 14-bit to 28-bit, Back (Type B)

COMMERCIAL TEMPERATURE RANGE

IDT74SSTUA32866

1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST

OPERATING CHARACTERISTICS, TA = 25ºC

(1,2)

Symbol Parameter Min. Typ. Max. Unit

VDD Supply Voltage 1.7 — 1.9 V

VREF Reference Voltage 0.49 * VDD 0.5 * VDD 0.51 * VDD V

VTT Termination Voltage VREF– 40mV VREF VREF+ 40mV V

VI Input Voltage 0 — VDD V

IH AC High-Level Input Voltage VREF+ 250mV — —

IL AC Low-Level Input Voltage Data Inputs, CSR, DCS,— — VREF– 250mV V

IH DC High-Level Input Voltage PAR_IN VREF+ 125mV — —

VIL DC Low-Level Input Voltage — — VREF– 125mV

VIH High-Level Input Voltage RESET, Cx 0.65 * VDD ——V

VIL Low-Level Input Voltage RESET, Cx — — 0.35 * VDD V

VICR Common Mode Input Voltage CLK, CLK 0.675 — 1.125 V

VID Differential Input Voltage CLK, CLK 600 — — mV

IOH High-Level Output Current Data Outputs, PPO — — –8 mA

IOL Low-Level Output Current Data Outputs, PPO, QERR —— 8

A Operating Free-Air Temperature 0 — 70 ° C

NOTES:

1. The RESET and Cx inputs of the device must be held at valid levels (not floating) to ensure proper device operation.

2. The differential inputs must not be floating unless RESET is LOW.

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VOH Output HIGH Voltage IOH = –6 mA 1.2 — — V

VOL Output LOW Voltage IOL = 6 mA — — 0.5 V

II All Inputs

(1)

VI = VDD or GND; VDD = 1.9V — — ±5 μA

DD Static Standby IO = 0, VDD = 1.9V, RESET = GND — — 100 μA

Static Operating IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH (AC) or VIL (AC) ——40mA

DDD Dynamic Operating IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH (AC) or VIL (AC),———μA/Clock

(Clock Only) CLK and CLK Switching 50% Duty Cycle. MHz

IO = 0, VDD = 1.8V, RESET = VDD, 1:1 Mode — — —

Dynamic Operating V

I = VIH (AC) or VIL (AC), CLK and CLK Switching at μA/Clock

(Per Each Data Input) 50% Duty Cycle. One Data Input Switching at 1:2 Mode — — — MHz/Data

Half Clock Frequency, 50% Duty Cycle. Input

Data Inputs, CSR, PAR_IN 2.5 — 3.5

I CLK and CLK VICR = 0.9V, VID = 600mV 2 — 3 pF

RESET VI = VDD or GND — — —

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:

Operating Condition: TA = 0°C to +70°C, VDD = 1.8V ± 0.1V

NOTE:

1. Each VREF pin (A3, T3) should be tested independently, with the other pin open circuit.

COMMERCIAL TEMPERATURE RANGE

IDT74SSTUA32866

1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST

TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR

TEMPERATURE RANGE

VDD = 1.8V ± 0.1V

Symbol Parameter Min. Max. Unit

fCLOCK Clock Frequency — 410 MHz

tw Pulse Duration, CLK, CLK HIGH or LOW 1 — ns

tACT

(1,2)

Differential Inputs Active Time — 10 ns

tINACT

(1,3)

Differential Inputs Inactive Time — 15 ns

DCS before CLK↑, CLK↓, CSR HIGH; CSR before CLK↑, CLK↓, DCS HIGH 0.7 —

SU Setup Time DCS before CLK↑, CLK↓, CSR LOW 0.5 — ns

DODT, DCKE, and data before CLK↑, CLK↓ 0.5 —

PAR_IN before CLK↑, CLK↓ 0.5 —

H Hold Time DCS , DODT, DCKE, and data after CLK↑, CLK↓ 0.5 — ns

PAR_IN after CLK↑, CLK↓ 0.5 —

NOTES:

1. This parameter is not production tested.

2. Data and VREF inputs must be low a minimum time of tACT max, after RESET is taken HIGH.

3. Data, VREF, and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max, after RESET is taken LOW.

SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING

RANGE (UNLESS OTHERWISE NOTED)

(1)

VDD = 1.8V ± 0.1V

Symbol Parameter Min Max. Unit

fMAX 410 — MHz

tPDM

(2)

CLK and CLK to Q 1.2 1.9 ns

tPDMSS

(2,3)

CLK and CLK to Q (simultaneous switching) — 2 ns

tRPHL RESET to Q — 3 ns

dV/dt_r Output slew rate from 20% to 80% 1 4 V/ns

dV/dt_f Output slew rate from 20% to 80% 1 4 V/ns

dV/dt_Δ

(4)

Output slew rate from 20% to 80% — 1 V/ns

tPD CLK and CLK to PPO 0.5

(5)

1.8

(5)

tPLH CLK and CLK to QERR 1.2

(5)

tPHL CLK and CLK to QERR 1

(5)

2.4

(5)

tRPHL RESET to PPO — 3 ns

tRPLH RESET to QERR — 3 ns

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS.

2. Includes 350ps of test load transmission line delay.

3. This parameter is not production tested.

4. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).

5. For reference only. Final values to be determined.

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74SSTUA32866BFG8

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Registers DDR II REGISTER

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74SSTUA32866BFG8

74SSTUA32866BFG8

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