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74SSTUA32866BFG8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
16
COMMERCIAL TEMPERATURE RANGE
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
CL = 30 pF
RL = 1KΩ
DUT
Out
RL = 100Ω
CLK Inputs
T
L = 50Ω
T
L = 350ps, 50Ω
Test Point
V
DD
0V
V
DD/2
LVCMOS
RESET
Input
IDD
VDD/2
tINACT
tACT
10%
90%
CLK
V
ICR
VID
tPLH tPHL
Output
V
OH
VOL
VICR
VTT VTT
VOH
VOL
VIH
VIL
tRPHL
VDD/2
V
TT
LVCMOS
RESET
Input
Output
VICR
VID
VICR
Input
tW
VREF
VIH
VIL
VREF
Input
VICR VID
tSU tH
CLK
CLK
VDD
RL = 1KΩ
Test Point
Test Point
CLK
CLK
CLK
TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V ± 0.1V)
Voltage Waveforms - Pulse Duration
NOTES:
1. CL includes probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA
3. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VTT = VREF = VDD/2
6. VIH = VREF + 250mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF - 250mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. VID = 600mV.
9. tPLH and tPHL are the same as tPDM.
Load Circuit
Voltage Waveforms - Setup and Hold Times
Voltage Waveforms - Propagation Delay Times
Voltage Waveforms - Propagation Delay Times
Voltage and Current Waveforms
Inputs Active and Inactive Times
17
COMMERCIAL TEMPERATURE RANGE
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
CL = 10 pF
RL = 50Ω
DUT
Out
Test Point
V
DD
VOH
80%
20%
VOL
Output
dv_f
dt_f
C
L = 10 pF
RL = 50Ω
DUT
Out
Test Point
VOL
20%
80%
VOH
Output
dv_r
dt_r
TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V ± 0.1V)
NOTES:
1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
Load Circuit: High-to-Low Slew-Rate Adjustment
Voltage Waveforms: High-to-Low Slew-Rate Adjustment
Load Circuit: Low-to-High Slew-Rate Adjustment
Voltage Waveforms: Low-to-High Slew-Rate Adjustment
18
COMMERCIAL TEMPERATURE RANGE
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
CL = 10 pF
RL = 1KΩ
DUT
Out
Test Point
V
DD
CL = 5 pF
RL = 1KΩ
DUT
Out
Test Point
VI(PP)
tPLH
Output
Waveform 1
V
CC
VOL
VCC/2
VICR
Timing
Inputs
VICR
VI(PP)
tPLH
Output
Waveform 2
V
OH
0V
VICR
0.15V
Timing
Inputs
VICR
tPLH
Output
Waveform 2
V
OH
0V
0.15V
LVCMOS
RESET
Input
V
CC
0V
VCC/2
VICR
VICR
VI(PP)
tPLH
Output
V
OH
VOL
CK
CK
tPLH
Output
V
TT
tPLH
Input
V
IH
VIL
VDD/2
LVCMOS RESET
VOH
VOL
VTT
TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V ± 0.1V)
Load Circuit: Partial-Parity-Out Load Circuit
Load Circuit:
QERR QERR
QERR QERR
QERR
Output
NOTES:
1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
Voltage Waveforms - Propagation Delay Times with with Respect
to Clock Inputs
Voltage Waveforms - Open-Drain Output LOW-to-HIGH Transition
Time with Respect to Reset Input
Voltage Waveforms - Open-Drain Output HIGH-to-LOW Transition
Time with Respect to Clock Inputs
Voltage Waveforms - Open-Drain Output LOW-to-HIGH Transition
Time with Respect to Clock Inputs
Voltage Waveforms - Propagation Delay Times with with Respect
to Reset Input
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

74SSTUA32866BFG8

Mfr. #:
Buy 74SSTUA32866BFG8
Manufacturer:
IDT
Description:
Registers DDR II REGISTER
Lifecycle:
New from this manufacturer.
Delivery:
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