12
LT1786F
APPLICATIONS INFORMATION
WUU
U
battery drain. Additionally, all components, including PC
board and hardware, usually must fit within the LCD
enclosure with a height restriction of 5mm to 10mm.
The CCFL regulator drives an inductor that acts as a
switched-mode current source for a current-driven Royer-
class converter with efficiencies as high as 90%. The
control loop forces the CCFL PWM to modulate the aver-
age inductor current to maintain constant current in the
lamp. The constant current value, and thus lamp intensity,
is programmable. This drive technique provides a wide
range of intensity control. A unique lamp-current pro-
gramming block permits either grounded lamp or floating
lamp configurations. Grounded lamp circuits directly sense
one-half of average lamp current. Floating lamp circuits
directly sense the Royer’s primary-side converter current.
Floating-lamp circuits provide symmetric differential drive
to the lamp and reduce the parasitic loss from stray lamp-
to-frame capacitance, extending illumination range.
Block Diagram Operation
The LT1786F is a fixed frequency, current mode switching
regulator. A fixed frequency, current mode switcher con-
trols switch duty cycle directly by switch current rather
than by output voltage. Referring to the block diagram for
the LT1786F, the switch turns ON at the start of each
oscillator cycle. The switch turns OFF when switch current
reaches a predetermined level. The control of output lamp
current is obtained by using the output of a unique
programming block to set current trip level. The current
mode switching technique has several advantages. First,
it provides excellent rejection of input voltage variations.
Second, it reduces the 90° phase shift at mid-frequencies
in the energy storage inductor. This simplifies closed-loop
frequency compensation under widely varying input
voltage or output load conditions. Finally, it allows simple
pulse-by-pulse current limiting to provide maximum
switch protection under output overload or short-circuit
conditions.
The LT1786F incorporates a low dropout internal regula-
tor that provides a 2.4V supply for most of the internal
circuitry. This low dropout design allows input voltage to
vary from 3V to 6.5V with little change in quiescent
current. An active low shutdown pin typically reduces total
supply current to 150µA by shutting off the 2.4V regulator
and locks out switching action for standby operation. The
IC incorporates undervoltage lockout by sensing regulator
dropout and locking out switching below about 2.5V. The
regulator also provides thermal shutdown protection that
locks out switching in the presence of excessive junction
temperatures.
A 200kHz oscillator is the basic clock for all internal timing.
The oscillator turns on the output switch via its own logic
and driver circuitry. Adaptive anti-sat circuitry detects the
onset of saturation in the power switch and adjusts base
drive current instantaneously to limit switch saturation.
This minimizes driver dissipation and provides rapid turn-
off of the switch. The CCFL power switch is guaranteed to
provide a minimum of 1.25A in the LT1786F. The antisat
circuitry provides a ratio of switch current to driver current
of about 50:1.
Digital Interface
The LT1786F communicates with an SMBus host using
the standard 2-wire SMBus interface. The Timing Diagram
shows the signals on the SMBus. The two bus lines SDA
and SCL must be high when the bus is not in use. External
pull-up resistors or current sources are required at these
lines.
The LT1786F is a receive-only (slave) device. The master
must apply the following Write Byte protocol to commu-
nicate with the LT1786F:
17 1181811
S Slave Address WR A Command Byte A Data Byte A P
S = Start Conditon, WR = Write Bit, A = Acknowledge Bit, P = Stop Condition
The master initiates communication with the LT1786F
with a START condition (see SMBus Operating Sequence)
and a 7-bit address followed by the write bit = 0. The
LT1786F acknowledges and the master delivers the
command byte. The LT1786F acknowledges and latches
the active bits of the command byte into register A (see
Block Diagram) at the falling edge of the acknowledge
pulse. The master sends the data byte and the LT1786F
acknowledges the data byte. The data byte is latched into
register C at the falling edge of the final acknowledge pulse
and the DAC current output assumes the new 6-bit data
