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LTC4441MPMSE#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
LTC4441/LTC4441-1
10
44411fa
Driver Output Stage
A simplified version of the LTC4441/LTC4441-1’s driver-
output stage is shown in Figure 2.
The pre-driver that drives Q1, P1 and N1 uses an adap-
tive method to minimize cross-conduction currents. This
is done with a 5ns nonoverlapping transition time. N1 is
fully turned off before Q1 is turned on and vice-versa using
this 5ns buffer time. This minimizes any cross-conduction
currents while Q1 and N1 are switching on and off without
affecting their rise and fall times.
Thermal Shutdown
The LTC4441/LTC4441-1 has a thermal detector that dis-
ables the DRV
CC
regulator and pulls the driver output low
when activated. If the junction temperature exceeds150°C,
the driver pull-up devices, Q1 and P1, turn off while the
pull-down device, N1, turns on briskly for 200ns to quickly
pull the output low. The thermal shutdown circuit has 20°C
of hysteresis.
Enable/Shutdown Input
The EN/SHDN pin serves two functions. Pulling this pin
below 0.45V forces the LTC4441/LTC4441-1 into shutdown
mode. In shutdown mode, the internal circuitry and the
DRV
CC
regulator are off and the supply current drops to
<12µA. If the input voltage is between 0.45V and 1.21V,
the DRV
CC
regulator and internal circuit power up but the
driver output stays low. If the input goes above 1.21V, the
driver starts switching according to the input logic signal.
The driver enable comparator has a small hysteresis of
120mV.
Blanking
In some switcher applications, a current sense resistor
is placed between the low side power MOSFET’s source
terminal and ground to sense the current in the MOSFET.
With this configuration, the switching controller must
incorporate some timing interval to blank the ringing
onthe current sense signal immediately after the MOSFET
is turned on. This ringing is caused by the parasitic induc-
tance and capacitance of the PCB trace and the MOSFET.
The duration of the ringing is thus dependent on the PCB
layout and the components used and can be longer than
the blanking interval provided by the controller.
applicaTions inForMaTion
Q1
P1
DRV
CC
N1
N3
DRV
CC
LTC4441
PGND
OUT
C
GD
V
IN
POWER
MOSFET
4441 F02
LOAD
INDUCTOR
C
GS
N2
R
O
Figure 2. Driver Output Stage
The pull-up device is the combination of an NPN transis-
tor, Q1, and a P-channel MOSFET, P1. This provides both
the ability to swing to rail (DRV
CC
) and deliver large peak
charging currents.
The pull-down device is an N-channel MOSFET, N1, with
a typical on resistance of 0.35Ω. The low impedance of
N1 provides fast turn-off of the external power MOSFET
and holds the power MOSFET’s gate low when its drain
voltage switches. When the power MOSFET’s gate is pulled
low (gate shorted to source through N1) by the LTC4441/
LTC4441-1, its drain voltage is pulled high by its load (e.g.,
inductor or resistor). The slew rate of the drain voltage
causes current to flow to the MOSFET’s gate through its
gate-to-drain capacitance. If the MOSFET driver does not
have sufficient sink current capability (low output imped-
ance), the current through the power MOSFET’s C
GD
can
momentarily pull the gate high and turn the MOSFET
back on.
A similar situation occurs during power-up when V
IN
is-
ramping up with the DRV
CC
regulator output still low. N1 is
off and the driver output, OUT, may momentarily pull high
through the power MOSFET’s C
GD
, turning on the power
MOSFET. The N-channel MOSFETs N2 and N3,shown in
Figure 2, prevent the driver output from going high in this
situation. If DRV
CC
is low, N3 is off. If OUT is pulled high
through the power MOSFET’s C
GD
, the gate of N2 gets
pulled high through RO. This turns N2 on, which then
pulls OUT low. Once DRV
CC
is >1V, N3 turns on to hold
the N2 gate low, thus disabling N2.
LTC4441/LTC4441-1
11
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The 10-Lead LTC4441 includes an open-drain output that
can be used to extend this blanking interval. The 8-Lead
LTC4441-1 does not have this blanking function. Figure 3
shows the BLANK pin connection. The BLANK pin is con-
nected directly to the switching controller’s SENSE
+
input.
Figure 4 shows the blanking waveforms. If the driver input
is low, the external power MOSFET is off and MB turns
on to hold SENSE
+
low. If the driver input goes high, the
power MOSFET turns on after the driver’s propagation
delay. MB remains on, attenuating the ringing seen by the
controller’s SENSE
+
input. After the programmed blanking
time, MB turns off to enable the current sense signal. MB
is designed to turn on and turn off at a controlled slew rate.
This is to prevent the gate switching noise from coupling
into the current sense signal.
applicaTions inForMaTion
Power Dissipation
To ensure proper operation and long-term reliability, the
LTC4441/LTC4441-1 must not operate beyond its maxi-
mum temperature rating. The junction temperature can
be calculated by:
I
Q(TOT)
= I
Q
+ ƒ • Q
G
P
D
= V
IN
• (I
Q
+ ƒ • Q
G
)
T
J
= T
A
+ P
D
• θ
JA
where:
I
Q
= LTC4441/LTC4441-1 static quiescent current,
typically 250µA
ƒ = Logic input switching frequency
Q
G
= Power MOSFET total gate charge at corre-
sponding V
GS
voltage equal to DRV
CC
V
IN
= LTC4441/LTC4441-1 input supply voltage
T
J
= Junction temperature
T
A
= Ambient temperature
θ
JA
= Junction-to-ambient thermal resistance. The
10-pin MSOP package has a thermal resistance of
θ
JA
= 38°C/W.
BLANK
SGND
RBLANK
POWER
MOSFET
LOAD
INDUCTOR
TO
SWITCHING
CONTROLLER’S
CURRENT
SENSE
INPUT
OUT
LTC4441
R4
V
IN
R3
4441 F03
SENSE
+
SENSE
–
KEEP THIS
TRACE SHORT
MB
DRIVER
LEADING
EDGE DELAY
R7
PGND
Figure 3. Blanking Circuit
Figure 4. Blanking Waveforms
BLANKING TIME
IN
OUT
MB GATE
BLANK/SENSE
+
4441 F04
POWER
MOSFET’s
CURRENT
POWER MOSFET’s
SOURCE TERMINAL
The blanking interval can be adjusted using resistor R7
connected to the RBLANK pin. A small resistance value
gives a shorter interval with a default minimum of 75ns.
The value of the resistor R4 and the on-resistance of MB
(typically 11Ω) form a resistive divider attenuating the
ringing. R4 needs to be large for effective blanking, but not
so large as to cause delay to the sense signal. A resistance
value of 1k to 10k is recommended.
For optimum performance, the LTC4441/LTC4441-1should
be placed as close as possible to the powerMOSFET and
current sense resistor, R3.
LTC4441/LTC4441-1
12
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applicaTions inForMaTion
The total supply current, I
Q(TOT)
, consists of the LTC4441/
LTC4441-1’s static quiescent current, I
Q
, and the current
required to drive the gate of the power MOSFET, with
thelatter usually much higher than the former. The dissi-
pated power, P
D
, includes the efficiency loss of the DRV
CC
regulator. With a programmed DRV
CC
, a high V
IN
results
in higher efficiency loss.
As an example, consider an application with V
IN
= 12V.
The switching frequency is 300kHz and the maximum
ambient temperature is 70°C. The power MOSFET chosen
is three pieces of IRFB31N20D, which has a maximum
R
DS(ON)
of 82mΩ (at room temperature) and a typical
total gatecharge of 70nC (the temperature coefficient of
the gate charge is low).
I
Q(TOT)
= 500µA + 210nC • 300kHz = 63.5mA
P
IC
= 12V • 63.5mA = 0.762W
T
J
= 70°C + 38°C/W • 0.762W = 99°C
This demonstrates how significant the gate charge cur-
rent can be when compared to the LTC4441/LTC4441-1’s
static quiescent current. To prevent the maximum junc-
tion temperature from being exceeded, the input supply
current must be checked when switching at high V
IN
. A
tradeoff between the operating frequency and the size of
the power MOSFET may be necessary to maintain areliable
LTC4441/LTC4441-1 junction temperature. Prior to lower-
ing the operating frequency, however, be sure to check with
power MOSFET manufacturers for their innovations on low
Q
G
, low R
DS(ON)
devices. Power MOSFET manufacturing
technologies are continually improving, with newer and
better performing devices being introduced.
PC Board Layout Checklist
When laying out the printed circuit board, the following-
checklist should be used to ensure proper operation of
the LTC4441/LTC4441-1:
A. Mount the bypass capacitors as close as possible be-
tween the DRV
CC
and PGND pins and between the V
IN
and SGND pins. The PCB trace loop areas should be
tightened as much as possible to reduce inductance.
B. Use a low inductance, low impedance ground plane to
reduce any ground drop. Remember that the LTC4441/
LTC4441-1 switches 6A peak current and any significant
ground drop will degrade signal integrity.
C. Keep the PCB ground trace between the LTC4441/
LTC4441-1 ground pins (PGND and SGND) and the
external current sense resistor as short and wide as
possible.
D. Plan the ground routing carefully. Know where the large
load switching current paths are. Maintain separate
ground return paths for the input pin and output pin
to avoid sharing small-signal ground with large load
ground return. Terminate these two ground traces only
at the GND pin of the driver (STAR network).
E. Keep the copper trace between the driver output pin
andthe load short and wide.
F. Place the small-signal components away from the high
frequency switching nodes. These components include
the resistive networks connected to the FB, RBLANK
and EN/SHDN pins.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

LTC4441MPMSE#PBF

Mfr. #:
Buy LTC4441MPMSE#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Gate Drivers N-Ch MOSFET Gate Drvr
Lifecycle:
New from this manufacturer.
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