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AD744JRZ

P1-P3P4-P6P7-P9P10-P12P13-P13
REV. C
AD744
–9–
Table II. Recommended Values of C
COMP
vs. Various Load Conditions for the Circuits of
Figures 31 and 32.
Max Slew –3 dB
R1 R2 Gain Gain C
LOAD
C
COMP
C
LEAD
Rate Bandwidth
(⍀)(⍀) Follower Inverter (pF) (pF) (pF) (V/␮s) (MHz)
4.99 k 4.99 k 2 1 50 0 7 75 2.5
1
4.99 k 4.99 k 2 1 150 5 7 37 2.3
1
4.99 k 4.99 k 2 1 1000 20 – 14 1.2
4.99 k 4.99 k 2 1 >2000 25 – 12.5
2
1.0
499 Ω 4.99 k 11 10 270 0 – 75 1.2
499 Ω 4.99 k 11 10 390 2 – 50 0.85
499 Ω 4.99 k 11 10 1000 5 – 37
2
0.60
NOTES
1
Bandwidth with C
LEAD
adjusted for minimum settling time.
2
Into large capacitive loads the AD744’s 25 mA output current limit sets the slew rate of the amplifier, in V/ µs, equal to 0.025
amps divided by the value of C
LOAD
in µF. Slew rate is specified into rated max C
LOAD
except for cases marked
2
, which are
specified with a 50 pF. load.
AD744
1␮F
0.1␮F
–V
S
C
COMP
1␮F
0.1␮F
+V
S
V
OUT
V
IN
OPTIONAL
R2*
C
LEAD
*
R1*
*SEE TABLE II
Figure 32. AD744 Connected as an Inverting Amplifier
Operating at Gains of 1 or Greater
Using Decompensation to Extend the Gain Bandwidth
Product
When the AD744 is used in applications where the closed-loop
gain is greater than 10, gain bandwidth product may be enhanced
by connecting a small capacitor between Pins 1 and 5 (Figure
33). At low frequencies, this capacitor cancels the effects of the
chip’s internal compensation capacitor, C
COMP
, effectively dec-
ompensating the amplifier.
Due to manufacturing variations in the value of the internal
C
COMP
, it is recommended that the amplifier’s response be
optimized for the desired gain by using a 2 to 10 pF trimmer
capacitor rather than using a fixed value.
\
AD744
1␮F
0.1␮F
–V
S
1␮F
0.1␮F
+V
S
V
OUT
V
IN
NOT CONNECTED
R2*
R1*
2 – 10pF
*SEE TABLE III
Figure 33. Using the Decompensation Connection to
Extend Gain Bandwidth
Table III. Performance Summary for the Circuit of Figure 33
R1 R2 Gain Gain –3 dB Gain/BW
(⍀)(⍀) Follower Inverter Bandwidth Product
1 k 10 k 11 10 2.5 MHz 25 MHz
100 10 k 101 100 760 kHz 76 MHz
100 100 k 1001 1000 225 kHz 225 MHz
REV. C
AD744
–10–
19.95k⍀
20k⍀
9.96k⍀
5k⍀
8k⍀
20V SPAN
10V SPAN
DAC OUT
POWER
GND
–V
EE
REF
GND
BIPOLAR
OFFSET
ADJUST
5k⍀
LSB
MSB
10V
V
CC
REF
OUT
REF
IN
0.1␮F
0.1␮F
100⍀
AD744
1␮F
+15V
1␮F
C
LEAD
10pF
–15V
100⍀
GAIN
ADJUST
AD565A
Figure 34.
±
10 V Voltage Output Bipolar DAC Using the AD744 as an Output Buffer
HIGH-SPEED OP AMP APPLICATIONS
AND TECHNIQUES
DAC Buffers (I-to-V Converters)
Digital-to-analog converters which use bipolar transistors to
switch currents into (or out of) their outputs can achieve very
fast settling times. The AD565A, for example, is specified to
settle to 12 bits in less than 250 ns, with a current output. How-
ever, in many applications, a voltage output is desirable, and it
would be useful – perhaps essential – that this I-to-V conversion
be accomplished without increasing the settling time or without
degrading the accuracy of the DAC.
Figure 34 is a schematic of an AD565A DAC using an AD744
output buffer. The 10 pF C
LEAD
capacitor compensates for the
DAC’s output capacitance, plus the 5.5 pF amplifier input
capacitance.
Figure 35 is an oscilloscope photo of the AD744’s output volt-
age with a +10 V to 0 V step applied; this corresponds to an all
“1s” to all “0s” code change on the DAC. Since the DAC is
Figure 35. Upper Trace: AD744 Output Voltage for
a +10 V to 0 V Step, Scale: 5 mV/div.
Lower Trace: Logic Input Signal, Scale: 5 V/div.
connected in the 20 V span mode, 1 LSB is equal to 4.88 mV.
Output settling time for the AD565/AD744 combination is less
than 500 ns to within a 2.44 mV, 1/2 LSB error band.
A HIGH-SPEED, 3 OP AMP INSTRUMENTATION
AMPLIFIER CIRCUIT
The instrumentation amplifier circuit shown in Figure 36 can
provide a range of gains from unity up to 1000 and higher. The
circuit bandwidth is 4 MHz at a gain of 1 and 750 kHz at a gain
of 10; settling time for the entire circuit is less than 2 µs
to within 0.01% for a 10 V step, (G = 10).
While the AD744 is not stable with 100% negative feedback (as
when connected as a standard voltage follower), phase margin
and therefore stability at unity gain may be increased to an accept-
able level by placing the parallel combination of a resistor and a
small lead capacitor between each amplifier’s output and its
inverting input terminal.
The only penalty associated with this method is a small band-
width reduction at low gains. The optimum value for C
LEAD
may be determined from the graph of Figure 41. This technique
can be used in the circuit of Figure 36 to achieve stable opera-
tion at gains from unity to over 1000.
AD744
+V
S
1␮F
1␮F
+15V
COMM
–15V
–V
S
1␮F
1␮F
0.1␮F
0.1␮F
PIN 7
PIN 4
EACH
AMPLIFIER
A1
–IN
10k⍀
7.5pF
**10k⍀
AD744
A3
7.5pF
**10k⍀
**10k⍀
5pF
**10k⍀
*1.5pF – 20pF
(TRIM FOR BEST SETTLING TIME)
SENSE
10k⍀
AD744
A2
+IN
REFERENCE
*VOLTRONICS SP20 TRIMMER CAPACITOR OR EQUIVALENT
**RATIO MATCHED 1% METAL FILM RESISTORS
20,000
R
G
CIRCUIT GAIN = + 1
FOR OPTIONAL OFFSET ADJUSTMENT:
TRIM A1, A3 USING TRIM PROCEDURE SHOWN IN FIGURE 21.
R
G
Figure 36. A High Performance, 3 Op Amp
Instrumentation Amplifier Circuit
REV. C
AD744
–11–
Table IV. Performance Summary for the 3 Op Amp
Instrumentation Amplifier Circuit
Gain RG Bandwidth T Settle (0.01%)
1 NC 3.5 MHz 1.5 µs
2 20 kΩ 2.5 MHz 1.0 µs
10 2.22 kΩ 1 MHz 2 µs
100 202 Ω 290 kHz 5 µs
Figure 37. The Pulse Response of the 3 Op Amp
Instrumentation Amplifier. Gain = 1, l Horizontal Scale:
0.5
µ
V/div., Vertical Scale: 5 V/div. (Gain= 10)
Figure 38. Settling Time of the 3 Op Amp Instrumentation
Amplifier. Horizontal Scale: 500 ns/div., Vertical Scale,
Pulse Input: 5 V/div., Output Settling: 1 mV/div.
Minimizing Settling Time in Real-World Applications
An amplifier with a “single pole” or “ideal” integrator open-loop
frequency response will achieve the minimum possible settling
time for any given unity-gain bandwidth. However, when this
“ideal” amplifier is used in a practical circuit, the actual settling
time is increased above the minimum value because of added
time constants which are introduced due to additional capacitance
on the amplifier’s summing junction. The following discussion
will explain how to minimize this increase in settling time by the
selection of the proper value for feedback capacitor, C
L
.
If an op amp is modeled as an ideal integrator with a unity gain
crossover frequency, f
O
, Equation 1 will accurately describe the
small signal behavior of the circuit of Figure 39. This circuit
models an op amp connected as an I-to-V converter.
Equation 1 would completely describe the output of the system
if not for the op amp’s finite slew rate and other nonlinear
effects. Even considering these effects, the fine scale settling to
<0.1% will be determined by the op amp’s small signal behav-
ior. Equation 1.
V
O
I
IN
=
–R
RC
L
+ C
X
()
2πF
O
s
2
+
G
N
2πF
O
+ RC
L
s +1
Where F
O
= the op amp’s unity gain crossover frequency
G
N
= the “noise” gain of the circuit 1 +
R
R
O
This Equation May Then Be Solved for C
L
:
Equation 2.
C
L
=
2 − G
N
R 2πF
O
+
2 RC
X
2πF
O
+ 1− G
N
()
R 2πF
O
In these equations, capacitance C
X
is the total capacitance appear-
ing at the inverting terminal of the op amp. When modeling an
I-to-V converter application, the Norton equivalent circuit of
Figure 39 can be used directly. Capacitance C
X
is the total capaci-
tance of the output of the current source plus the input capacitance
of the op amp, which includes any stray capacitance at the op
amp’s input.
AD744
C
L
V
OUT
R
O
R
C
COMP
(OPTIONAL)
C
X
I
O
R
L
C
LOAD
Figure 39. A Simplified Model of the AD744 Used as a
Current-to-Voltage Converter
When R
O
and I
O
are replaced with their Thevenin V
IN
and R
IN
equivalents, the general purpose inverting amplifier model of
Figure 40 is created. Here capacitor C
X
represents the input
capacitance of the AD744 (5.5 pF) plus any stray capacitance
due to wiring and the type of IC package employed.
AD744
C
L
V
OUT
R
IN
R
C
COMP
(OPTIONAL)
C
X
V
IN
R
L
C
LOAD
Figure 40. A Simplified Model of the AD744 Used
as an Inverting Amplifier
P1-P3P4-P6P7-P9P10-P12P13-P13

AD744JRZ

Mfr. #:
Buy AD744JRZ
Manufacturer:
Analog Devices Inc.
Description:
Precision Amplifiers Prec 500ns Settling BiFET
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