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AD744KNZ

P1-P3P4-P6P7-P9P10-P12P13-P13
REV. C
AD744
–6–
–Typical Characteristics
Figure 19. Settling Time vs. Closed
Loop Voltage Gain
Figure 22a. Unity-Gain Follower
Figure 23a. Unity-Gain Inverter
Figure 20. THD Test Circuit
Figure 22b. Unity-Gain Follower
Large Signal Pulse Response,
C
COMP
= 5 pF
Figure 23b. Unity-Gain Inverter Large
Signal Pulse Response, C
COMP
= 5 pF
Figure 21. Offset Null Configuration
Figure 22c. Unity-Gain Follower
Small Signal Pulse Response,
C
COMP
= 5 pF
Figure 23c. Unity-Gain Inverter Small
Signal Pulse Response, C
COMP
= 0 pF
REV. C
AD744
–7–
POWER SUPPLY BYPASSING
The power supply connections to the AD744 must maintain a
low impedance to ground over a bandwidth of 10 MHz or more.
This is especially important when driving a significant resistive
or capacitive load, since all current delivered to the load comes
from the power supplies. Multiple high quality bypass capacitors
are recommended for each power supply line in any critical
application. A 0.1 µF ceramic and a 1 µF electrolytic capacitor
as shown in Figure 24 placed as close as possible to the ampli-
fier (with short lead lengths to power supply common) will
assure adequate high frequency bypassing, in most applica-
tions. A minimum bypass capacitance of 0.1 µF should be used
for any application.
AD744
1␮F
0.1␮F
–V
S
1␮F
0.1␮F
+V
S
Figure 24. Recommended Power Supply Bypassing
MEASURING AD744 SETTLING TIME
The photos of Figures 26 and 27 show the dynamic response of
the AD744 while operating in the settling time test circuit of
Figure 25. The input of the settling time fixture is driven by a
flat-top pulse generator. The error signal output from the false
summing node of A1, the AD744 under test, is clamped, ampli-
fied by op amp A2 and then clamped again.
TO
TEKTRONIX
7A26
OSCILLOSCOPE
PREAMP
INPUT SECTION
(VIA LESS THAN 1 FT 50⍀
COAXIAL CABLE)
+15V
COM
–15V
+V
S
–V
S
1M⍀ 20pF
A2
AD3554
10k⍀
5pF
10k⍀
1.1k⍀
+V
S
–V
S
0.47␮F
0.47␮F
2X
HP2835
0.2pF – 0.8pF
206⍀
2X
HP2835
+V
S
–V
S
1␮F
0.1␮F
5pF – 18pF
10k⍀
AD744
A1
5k⍀
1␮F
0.1␮F
10pF
4.99k⍀
200⍀
4.99k⍀
NULL
FLAT-TOP
PULSE
GENERATOR
DATA
DYNAMICS
5109
OR
EQUIVALENT
NOTE: USE CIRCUIT BOARD WITH GROUND PLANE
V
ERROR
ⴛ 10
V
IN
Figure 25. Settling Time Test Circuit
The error signal is thus clamped twice: once to prevent overloading
amplifier A2 and then a second time to avoid overloading the
oscilloscope preamp. A Tektronix oscilloscope preamp type
7A26 was carefully chosen because it recovers from the
approximately 0.4 V overload quickly enough to allow accurate
measurement of the AD744’s 500 ns settling time. Amplifier A2
is a very high-speed FET-input op amp; it provides a voltage
gain of 10, amplifying the error signal output of the AD744
under test.
Figure 26. Settling Characteristics 0 to +10 V Step
Upper Trace: Output of AD744 Under Test (5 V/div.)
Lower Trace: Amplified Error Voltage (0.01%/div.)
Figure 27. Settling Characteristics 0 to –10 V Step
Upper Trace: Output of AD744 Under Test (5 V/div.)
Lower Trace: Amplified Error Voltage (0.01%/div.)
REV. C
AD744
–8–
EXTERNAL FREQUENCY COMPENSATION
Even though the AD744 is useable without compensation in
most applications, it may be externally compensated for even
more flexibility. This is accomplished by connecting a capacitor
between Pins 5 and 8. Figure 28, a simplified schematic of the
AD744, shows where this capacitor is connected. This feature is
useful because it allows the AD744 to be used as a unity gain
voltage follower. It also enables the amplifier to drive capacitive
loads up to 2000 pF and greater.
5pF
+IN
300⍀
–IN
NULL /
COMPENSATION
NULL /
DECOMPENSATION
300⍀
COMPENSATION
2mA400␮A
+V
S
OUTPUT
–V
S
1k⍀1k⍀ 8k⍀
Figure 28. AD744 Simplified Schematic
The slew rate and gain bandwidth product of the AD744 are in-
versely proportional to the value of the compensation capacitor,
C
COMP
. Therefore, when trying to maximize the speed of the
amplifier, the value of C
COMP
should be minimized. C
COMP
can
also be used to slow the amplifier to a point where the slew rate
is perfectly symmetrical and well controlled. Figure 29 sum-
marizes the effect of external compensation on slew rate and
bandwidth.
C
COMP
– pF
2
0
GAIN BANDWIDTH – MHz
20
0.02
0.2
10 100 1000
10
SLEW RATE – V/␮s
100
0.1
1.0
Figure 29. Gain Bandwidth and Slew Rate vs. C
COMP
The following section provides tables to show what C
COMP
values
will provide the necessary compensation for given circuit configurations
and capacitive loads. In each case, the recommended C
COMP
is a
minimum value. A larger C
COMP
can always be used, but slew rate
and bandwidth performance will be degraded.
Figure 30 shows the AD744 configured as a unity gain voltage
follower. In this case, a minimum compensation capacitor of
5 pF is necessary for stable operation. Larger compensation ca-
pacitors can be used for driving larger capacitive loads. Table I
outlines recommended minimum values for C
COMP
based on
the desired capacitive load. It also gives the slew rate and band-
width that will be achieved for each case.
AD744
1␮F 0.1␮F
–V
S
C
COMP
5pF
1␮F 0.1␮F
+V
S
V
OUT
V
IN
Figure 30. AD744 Connected as a Unity Gain
Voltage Follower
Table I. Recommended Values of C
COMP
vs.
Various Capacitive Loads
Max –3 dB
C
LOAD
C
COMP
Slew Rate Bandwidth
Gain (pF) (pF) (V/␮s) (MHz)
1 50 5 37 6.5
1 150 10 25 4.3
1 2000 25 12.5 2.0
Figures 31 and 32 show the AD744 as a voltage follower
with gain and as an inverting amplifier. In these cases, external
compensation is not necessary for stable operation. How-
ever, compensation may be applied to drive capacitive loads
above 50 pF. Table II gives recommended C
COMP
values, along
with expected slew rates and bandwidths for a variety of load
conditions and gains for the circuits in Figures 31 and 32.
AD744
1␮F
0.1␮F
–V
S
C
COMP
1␮F
0.1␮F
+V
S
V
OUT
V
IN
OPTIONAL
R2*
C
LEAD
*
R1*
*SEE TABLE II
Figure 31. AD744 Connected as a Voltage Follower
Operating at Gains of 2 or Greater
P1-P3P4-P6P7-P9P10-P12P13-P13

AD744KNZ

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Buy AD744KNZ
Manufacturer:
Analog Devices Inc.
Description:
Precision Amplifiers Prec 500ns Settling BiFET
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