74HC_HCT174 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 16 April 2013 7 of 18
NXP Semiconductors
74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger
t
PHL
HIGH to LOW
propagation
delay
MR to Qn; see Figure 8
V
CC
= 2.0 V - 44 150 - 190 - 225 ns
V
CC
= 4.5 V - 16 30 - 38 - 45 ns
V
CC
= 5.0 V; C
L
=15pF - 13 - - - - - ns
V
CC
= 6.0 V - 13 26 - 33 - 38 ns
t
t
transition time Qn output; see Figure 7
[2]
V
CC
= 2.0 V - 19 75 - 95 - 110 ns
V
CC
= 4.5 V - 7 15 - 19 - 22 ns
V
CC
= 6.0 V - 6 13 - 16 - 19 ns
t
W
pulse width CP input HIGH or LOW;
see Figure 7
V
CC
= 2.0 V 80 17 - 100 - 120 - ns
V
CC
= 4.5 V 16 6 - 20 - 24 - ns
V
CC
= 6.0 V 14 5 - 17 - 20 - ns
MR
input LOW;
see Figure 8
V
CC
= 2.0 V 80 12 - 100 - 120 - ns
V
CC
= 4.5 V 16 4 - 20 - 24 - ns
V
CC
= 6.0 V 14 3 - 17 - 20 - ns
t
rec
recovery time MR to CP; see Figure 8
V
CC
= 2.0 V 5 11 - 5 - 5 - ns
V
CC
= 4.5 V 5 4- 5 - 5 - ns
V
CC
= 6.0 V 5 3- 5 - 5 - ns
t
su
set-up time Dn to CP; see Figure 7
V
CC
= 2.0 V 60 6 - 75 - 90 - ns
V
CC
= 4.5 V 12 2 - 15 - 18 - ns
V
CC
= 6.0 V 10 2 - 13 - 15 - ns
t
h
hold time Dn to CP; see Figure 7
V
CC
= 2.0 V 3 6- 3 - 3 - ns
V
CC
= 4.5 V 3 2- 3 - 3 - ns
V
CC
= 6.0 V 3 2- 3 - 3 - ns
f
max
maximum
frequency
CP input; see Figure 7
V
CC
= 2.0 V 6 30 - 5 - 4 - MHz
V
CC
= 4.5 V 30 90 - 24 - 20 - MHz
V
CC
= 6.0 V 35 107 - 28 - 24 - MHz
V
CC
= 5.0 V; C
L
=15pF - 99 - - - - - MHz
C
PD
power
dissipation
capacitance
per package;
V
I
=GNDtoV
CC
[3]
-17- - - - - pF
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit, see Figure 9
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC_HCT174 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 16 April 2013 8 of 18
NXP Semiconductors
74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger
[1] t
pd
is the same as t
PHL
and t
PLH
.
[2] t
t
is the same as t
THL
and t
TLH
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
= C
PD
V
CC
2
f
i
+ (C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
(C
L
V
CC
2
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V.
74HCT174
t
pd
propagation
delay
CP to Qn; see Figure 7
[1]
V
CC
= 4.5 V - 21 35 - 44 - 53 ns
V
CC
= 5.0 V; C
L
=15pF - 18 - - - - - ns
t
PHL
HIGH to LOW
propagation
delay
MR to Qn; see Figure 8
V
CC
= 4.5 V - 20 35 - 44 - 53 ns
V
CC
= 5.0 V; C
L
=15pF - 17 - - - - - ns
t
t
transition time Qn output; see Figure 7
[2]
V
CC
= 4.5 V - 7 15 - 19 - 22 ns
t
W
pulse width CP input; see Figure 7
V
CC
= 4.5 V 16 7 - 20 - 24 - ns
MR
input LOW;
see Figure 8
V
CC
= 4.5 V 20 7 - 25 - 30 - ns
t
rec
recovery time MR to CP; see Figure 8
V
CC
= 4.5 V 12 3 - 15 - 18 - ns
t
su
set-up time Dn to CP; see Figure 7
V
CC
= 4.5 V 16 4 - 20 - 24 - ns
t
h
hold time Dn to CP; see Figure 7
V
CC
= 4.5 V 5 3- 5 - 5 - ns
f
max
maximum
frequency
CP input; see Figure 7
V
CC
= 4.5 V 30 63 - 24 - 20 - MHz
V
CC
= 5.0 V; C
L
=15pF - 69 - - - - - MHz
C
PD
power
dissipation
capacitance
per package;
V
I
=GNDtoV
CC
1.5 V
[3]
-17- - - - - pF
Table 7. Dynamic characteristics
…continued
GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit, see Figure 9
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC_HCT174 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 16 April 2013 9 of 18
NXP Semiconductors
74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger
11. Waveforms
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 7. Input to output propagation delay, output transition time, clock input pulse width, set-up and hold times
for data input and maximum frequency
DDD
W
K
W
K
W
VX
W
VX
W
3+/
W
7+/
W
7/+
W
3/+
W
:
I
PD[
9
0
9
0
9
0
9
0
9
,
9
,
9
2+
9
2/
*1'
*1'
'QLQSXW
&
3LQSXW
4QRXWSXW


 
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 8. Master reset to output propagation delays, master reset pulse width and master reset to clock recovery
time
DDD
W
UHF
W
3+/
W
:
9
0
9
0
9
0
9
0
9
,
*1'
9
,
*1'
05
LQSXW
&
3LQSXW
9
2+
9
2/
4QRXWSXW

74HCT174N,652

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Flip Flops HEX D F/F MASTER RST
Lifecycle:
New from this manufacturer.
Delivery:
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