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FN7349.2
May 14, 2007
Applications Information
Product Description
The EL7158 is a high performance 40MHz pin driver. It
contains two analog switches connecting VH and VL to OUT.
Depending on the value of the IN pin, one of the two
switches will be closed and the other switch open. An output
enable (OE) is also supplied which opens both switches
simultaneously.
Due to the topology of the EL7158, both the VH and VL pins
can be connected to any voltage between the VS+ and VS-
pins, but VH must be greater than VL in order to prevent
turning on the body diode at the output stage.
Three-State Operation
When the OE pin is low, the output is three-state (floating).
The output voltage is the parasitic capacitance’s voltage. It
can be any voltage between VH and VL, depending on the
previous state. At three-state, the output voltage can be
pushed to any voltage between VH and V
L
. The output
voltage can’t be pushed higher than VH or lower than VL
since the body diode at the output stage will turn on.
Supply Voltage Range and Input Compatibility
The EL7158 is designed for operation on supplies from 5V to
18V (4.5V to 18V maximum). Table 2 shows the
specifications for the relationship between the VS+, VS-, VH,
VL, and GND pins.
All input pins are compatible with both 3V and 5V CMOS
signals. With a positive supply (V
S
+) of 5V, the EL7158 is
also compatible with TTL inputs.
Power Supply Bypassing
When using the EL7158, it is very important to use adequate
power supply bypassing. The high switching currents
developed by the EL7158 necessitate the use of a bypass
capacitor between the supplies (V
S
+ and V
S
-) and GND
pins. It is recommended that a 2.2µF tantalum capacitor be
used in parallel with a 0.1µF low-inductance ceramic MLC
capacitor. These should be placed as close to the supply
pins as possible. It is also recommended that the V
H
and V
L
pins have some level of bypassing, especially if the EL7158
is driving highly capacitive loads.
Power Dissipation Calculation
When switching at high speeds, or driving heavy loads, the
EL7158 drive capability is limited by the rise in die
temperature brought about by internal power dissipation. For
reliable operation die temperature must be kept below
T
JMAX
(+125°C). It is necessary to calculate the power
dissipation for a given application prior to selecting the
package type.
Power dissipation may be calculated:
where:
V
S
is the total power supply to the EL7158 (from V
S
+ to
GND)
V
OUT
is the swing on the output (V
H
- V
L
)
C
L
is the load capacitance
C
INT
is the internal load capacitance (100pF max)
I
S
is the quiescent supply current (3mA max)
f is frequency
Having obtained the application’s power dissipation, a
maximum package thermal coefficient may be determined,
to maintain the internal die temperature below T
JMAX
:
where:
T
JMAX
is the maximum junction temperature (+125°C)
T
MAX
is the maximum operating temperature
PD is the power dissipation calculated above
θ
JA
thermal resistance on junction to ambient
θ
JA
is 160°C/W for the SOIC8 package when using a
standard JEDEC JESD51-3 single-layer test board. If T
JMAX
is greater than +125°C when calculated using Equation 2 ,
then one of the following actions must be taken:
Reduce θ
JA
the system by designing more heat-sinking
into the PCB (as compared to the standard JEDEC
JESD51-3)
De-rate the application either by reducing the switching
frequency, the capacitive load, or the maximum operating
(ambient) temperature (T
MAX
)
PD V
S
( I
S
) C
INT
( V
S
2
f) C
L
( V
OUT
2
f)××+××+×=
(EQ. 1)
θ
JA
T
JMAX
T
MAX
–
PD
-----------------------------------------
=
(EQ. 2)
EL7158
