1. General description
The 74LV139 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC139 and 74HCT139.
The 74LV139 is a dual 2-to-4 line decoder/demultiplexer. It has two independent
decoders, each accepting two binary weighted inputs (nA0 and nA1) and providing four
mutually exclusive outputs (nY0 to nY3) that are LOW when selected. Each decoder has
an active LOW input (nE). When nE is HIGH, every output is forced HIGH. The enable
input can be used as the data input for a 1-to-4 demultiplexer application.
2. Features
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25 °C
Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
=25°C
Demultiplexing capability
Two independent 2-to-4 line decoders
Multifunction capability
Active LOW mutually exclusive outputs
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 °Cto+85°C and from 40 °C to +125 °C
3. Ordering information
74LV139
Dual 2-to-4 line decoder/demultiplexer
Rev. 04 — 13 December 2007 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LV139N 40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74LV139D 40 °C to +125 °C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74LV139_4 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 04 — 13 December 2007 2 of 16
NXP Semiconductors
74LV139
Dual 2-to-4 line decoder/demultiplexer
4. Functional diagram
74LV139DB 40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74LV139PW 40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74LV139BQ 40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
SOT763-1
Table 1. Ordering information
…continued
Type number Package
Temperature range Name Description Version
a) demultiplexer
b) decoder
Fig 1. Logic symbol Fig 2. IEC logic symbol
mna779
1A0
1A1
2A0
2A1
2E
1E
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
1
15
9
10
11
12
7
6
5
4
13
14
3
2
mna781
4
3
2
1
0
1
DX
5
6
7
0
1
2
3
G
0
3
12
13
14
1
0
15
DX
(a) (b)
11
10
9
0
1
2
3
G
0
3
4
3
2
2
EN
EN
1
1
X/Y
5
6
7
0
1
2
3
12
13
14
2
1
15
X/Y
11
10
9
0
1
2
3
Fig 3. Functional diagram
mna780
1Y0
1Y1
1Y2
1Y3
7
6
5
4
1A0
1A1
1E
1
3
2
2Y0
2Y1
2Y2
2Y3
9
10
11
12
2A0
2A1
2E
15
13
14
DECODER
DECODER
74LV139_4 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 04 — 13 December 2007 3 of 16
NXP Semiconductors
74LV139
Dual 2-to-4 line decoder/demultiplexer
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration DIP16, SO16 and (T)SSOP16 Fig 5. Pin configuration DHVQFN16
139
1E V
CC
1A0 2E
1A1 2A0
1Y0 2A1
1Y1 2Y0
1Y2 2Y1
1Y3 2Y2
GND 2Y3
001aad029
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
001aah107
74LV139
1Y3 2Y2
1Y2 2Y1
1Y1 2Y0
1Y0 2A1
1A1 2A0
1A0 2E
GND
2Y3
1E
V
CC
Transparent top view
7 10
6 11
5 12
4 13
3 14
2 15
8
9
1
16
terminal 1
index area
V
CC
(1)
Table 2. Pin description
Symbol Pin Description
1
E 1 enable input (active LOW)
1A0 2 address input
1A1 3 address input
1
Y0 4 output
1
Y1 5 output
1
Y2 6 output
1
Y3 7 output
GND 8 ground (0 V)
2
Y3 9 output
2
Y2 10 output
2
Y1 11 output
2
Y0 12 output
2A0 14 address input
2A1 13 address input
2
E 15 enable input (active LOW)
V
CC
16 supply voltage

74LV139D,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Encoders, Decoders, Multiplexers & Demultiplexers DUAL 2-4 LINE
Lifecycle:
New from this manufacturer.
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