Data Sheet AD5111/AD5113/AD5115
Rev. B | Page 7 of 24
ELECTRICAL CHARACTERISTICS—AD5115
10 kΩ and 80 kΩ versions: V
DD
= 2.3 V to 5.5 V, V
A
= V
DD
, V
B
= 0 V, −40°C < T
A
< +125°C, unless otherwise noted.
Table 4.
Parameter Symbol Test Conditions/Comments Min Typ
1
Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution N 5 Bits
Resistor Integral Nonlinearity
2
R-INL −0.5 +0.5 LSB
Resistor Differential Nonlinearity
2
R-DNL −0.25 +0.25 LSB
Nominal Resistor Tolerance ΔR
AB
/R
AB
−8 +8 %
Resistance Temperature Coefficient
3
(ΔR
AB
/R
AB
)/ΔT × 10
6
35 ppm/°C
Wiper Resistance
R
W
Code = zero scale 70 140 Ω
R
BS
Code = bottom scale 45 80 Ω
R
TS
Code = top scale 70 140 Ω
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Integral Nonlinearity
4
INL −0.25 +0.25 LSB
Differential Nonlinearity
4
DNL −0.25 +0.25 LSB
Full-Scale Error V
WFSE
R
AB
= 10 kΩ −1 LSB
R
AB
= 80 kΩ −0.5 LSB
Zero-Scale Error V
WZSE
R
AB
= 10 kΩ 1 LSB
R
AB
= 80 kΩ 0.25 LSB
Voltage Divider Temperature Coefficient
3
(ΔV
W
/V
W
)/ΔT × 10
6
Code = half scale ±10 ppm/°C
RESISTOR TERMINALS
Maximum Continuous I
A
, I
B
, and I
W
Current
3
R
AB
= 10 kΩ −6 +6 mA
R
AB
= 80 kΩ −1.5 +1.5 mA
Terminal Voltage Range
5
GND V
DD
V
Capacitance A, Capacitance B
3, 6
C
A
, C
B
f = 1 MHz, measured to GND,
code = half scale
20 pF
Capacitance W
3, 6
C
W
f = 1 MHz, measured to GND,
code = half scale
35 pF
Common-Mode Leakage Current
3
V
A
= V
W
= V
B
−500 ±15 +500 nA
DIGITAL INPUTS
Input Logic
3
High V
INH
2 V
Low V
INL
0.8 V
Input Current
3
I
N
±1 μA
Input Capacitance
3
C
IN
5 pF
POWER SUPPLIES
Single-Supply Power Range 2.3 5.5 V
Positive Supply Current I
DD
V
IH
= V
DD
or V
IL
= GND, V
DD
= 5 V 0.75 3.5 μA
V
IH
= V
DD
or V
IL
= GND, V
DD
= 2.7 V 2.5 μA
V
IH
= V
DD
or V
IL
= GND, V
DD
= 2.3 V 2.4 μA
EEMEM Store Current
3, 7
I
DD_NVM_STORE
2 mA
EEMEM Read Current
3, 8
I
DD_NVM_READ
320 μA
Power Dissipation
9
P
DISS
V
IH
= V
DD
or V
IL
= GND 5 μW
Power Supply Rejection
3
PSR ∆V
DD
/∆V
SS
= 5 V ± 10%
R
AB
= 10 kΩ −50 dB
R
AB
= 80 kΩ −64 dB
AD5111/AD5113/AD5115 Data Sheet
Rev. B | Page 8 of 24
Parameter Symbol Test Conditions/Comments Min Typ
1
Max Unit
DYNAMIC CHARACTERISTICS
3, 10
Bandwidth BW Code = half scale, −3 dB
R
AB
= 10 kΩ
2 MHz
R
AB
= 80 kΩ
200 kHz
Total Harmonic Distortion THD V
A
= V
DD
/2 + 1 V rms, V
B
= V
DD
/2,
f = 1 kHz, code = half scale
R
AB
= 10 kΩ −80 dB
R
AB
= 80 kΩ −85 dB
V
W
Settling Time t
s
V
A
= 5 V, V
B
= 0 V, ±0.5 LSB error
band
R
AB
= 10 kΩ
2.7
μs
R
AB
= 80 kΩ
9.5
μs
Resistor Noise Density e
N_WB
Code = half scale, T
A
= 25°C,
f = 100 kHz
R
AB
= 10 kΩ 9
nV/√Hz
R
AB
= 80 kΩ 20
V
FLASH/EE MEMORY RELIABILITY
3
Endurance
11
T
A
= 25°C 1 MCycles
100 kCycles
Data Retention
12
50
Years
1
Typical values represent average readings at 25°C, V
DD
= 5 V, V
SS
= 0 V, and V
LOGIC
= 5 V.
2
R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step
change from ideal between successive tap positions. The maximum wiper current is limited to 0.8 × V
DD
/R
AB
.
3
Guaranteed by design and characterization; not subject to production test.
4
INL and DNL are measured at V
WB
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
A
= V
DD
and V
B
= 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on current direction with respect to each other.
6
C
A
is measured with V
W
= V
A
= 2.5 V, C
B
is measured with V
W
= V
B
= 2.5 V, and C
W
is measured with V
A
= V
B
= 2.5 V.
7
Different from operating current; supply current for NVM program lasts approximately 30 ms.
8
Different from operating current; supply current for NVM read lasts approximately 20 μs.
9
P
DISS
is calculated from (I
DD
× V
DD
).
10
All dynamic characteristics use V
DD
= 5.5 V and V
LOGIC
= 5 V.
11
Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C.
12
Retention lifetime equivalent at junction temperature (T
J
) is 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
Data Sheet AD5111/AD5113/AD5115
Rev. B | Page 9 of 24
INTERFACE TIMING SPECIFICATIONS
V
DD
= 2.3 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 5.
Parameter Test Conditions/Comments Min Typ Max Unit Description
f
CLK
V
DD
2.7 V 50 MHz Clock frequency
V
DD
< 2.7 V 25 MHz
t
1
25 ns
CS
setup time
t
2
V
DD
2.7 V 10 ns
CLK
low time
V
DD
< 2.7 V 20 ns
t
3
V
DD
2.7 V
10
ns
CLK
high time
V
DD
< 2.7 V 20 ns
t
4
15 ns U/
D
setup time
t
5
6 ns U/
D
hold time
t
6
V
DD
2.7 V 20 ns
CS
rise to
CLK
hold time
V
DD
< 2.7 V 40 ns
t
7
15 ns
CS
rising edge to next
CLK
ignored
t
8
V
DD
2.7 V 12 ns U/
D
minimum pulse time
V
DD
< 2.7 V 24 ns
t
9
12 ns U/
D
rise to
CLK
falling edge
t
10
1 µs Minimum
CS
time
t
EEPROM_PROGRAM
1
15 50 ms Memory program time
t
POWER_UP
2
50 µs Power-on EEPROM restore time
1
EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles.
2
Maximum time after V
DD
is equal to 2.3 V.
TIMING DIAGRAMS
t
1
R
WB
CLK
CS
U/D
t
2
t
4
t
5
t
6
t
3
t
10
t
7
09654-002
Figure 2. Increment/Decrement Mode Timing
DATA
EEPROM
NEW DATA
t
EEPROM_PROGRAM
t
1
CLK
CS
U/D
t
8
t
6
09654-003
Figure 3. Storage Mode Timing
CS
CLK
U/D
t
1
t
9
t
6
09654-004
Figure 4. Shutdown Mode Timing

AD5111BCPZ80-500R7

Mfr. #:
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Description:
Digital Potentiometer ICs SGL CH128-Position I2C
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