13
LTC1159
LTC1159-3.3/LTC1159-5
the same process as in conventional applications, using
either the internal divider (LTC1159-3.3, LTC1159-5) or an
external divider with the adjustable version.
Figure 15 in the Typical Applications shows a synchronous
12V to –12V converter that can supply up to 1A with better
than 85% efficiency. By grounding the EXTV
CC
pin in the
Figure 15 circuit, the entire 12V output voltage is placed
across the driver and control circuits since the LTC1159
ground pins are at –12V. During start-up or short-circuit
conditions, operating power is supplied by the internal
4.5V regulator. The shutdown signal is level-shifted to the
negative output rail by Q3, and Q4 ensures that Q1 and Q2
remain off during the entire shutdown sequence.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100 – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1159 circuits: 1) LTC1159 V
IN
current, 2)
LTC1159 V
CC
current, 3) I
2
R losses and 4) P-channel
transition losses.
1. LTC1159 V
IN
current is the DC supply current given in
the electrical characteristics which excludes MOSFET driver
and control currents. V
IN
current results in a small (<1%)
loss which increases with V
IN
.
2. LTC1159 V
CC
current is the sum of the MOSFET driver
and control circuit currents. The MOSFET driver current
results from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from low
to high to low again, a packet of charge dQ moves from V
CC
to ground. The resulting dQ/dt is a current out of V
CC
which
is typically much larger than the control circuit current. In
continuous mode, I
GATECHG
f (Q
P
+ Q
N
), where Q
P
and Q
N
are the gate charges of the two MOSFETs.
By powering EXTV
CC
from an output-derived source, the
additional V
IN
current resulting from the driver and control
currents will be scaled by a factor of (Duty Cycle)/(Effi-
ciency). For example in a 20V to 5V application, 10mA of
V
CC
current results in approximately 3mA of V
IN
current.
This reduces the mid-current loss from 10% or more (if the
driver was powered directly from V
IN
) to only a few percent.
3. I
2
R losses are easily predicted from the DC resistances
of the MOSFET, inductor and current shunt. In continuous
mode all of the output current flows through L and
R
SENSE
, but is “chopped” between the P-channel and
N-channel MOSFETs. If the two MOSFETs have approxi-
mately the same R
DS(ON)
, then the resistance of one
MOSFET can simply be summed with the resistances of L
and R
SENSE
to obtain I
2
R losses. For example, if each
R
DS(ON)
= 0.1, R
L
= 0.15, and R
SENSE
= 0.05, then
the total resistance is 0.3. This results in losses ranging
from 3% to 12% as the output current increases from
0.5A to 2A. I
2
R losses cause the efficiency to roll-off at
high output currents.
4. Transition losses apply only to the P-channel MOSFET,
and only when operating at high input voltages (typically
20V or greater). Transition losses can be estimated from:
Transition Loss 5(V
IN
)
2
(I
MAX
)(C
RSS
)(f)
Other losses including C
IN
and C
OUT
ESR dissipative losses,
Schottky conduction losses during dead time, and inductor
core losses, generally account for less than 2% total
additional loss.
Auxiliary Windings—Suppressing Burst Mode
Operation
The LTC1159 synchronous switch removes the normal
limitation that power must be drawn from the inductor
primary winding in order to extract power from auxiliary
windings. With synchronous switching, auxiliary out-
puts may be loaded without regard to the primary output
load, providing that the loop remains in continuous
mode operation.
Burst Mode operation can be suppressed at low output
currents with a simple external network that cancels the
0.025V minimum current comparator threshold. This tech-
nique is also useful for eliminating audible noise from
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14
LTC1159
LTC1159-3.3/LTC1159-5
certain types of inductors in high current (I
OUT
> 5A)
applications when they are lightly loaded.
An external offset is put in series with the SENSE
pin to
subtract from the built-in 0.025V offset. An example of this
technique is shown in Figure 7. Two 100 resistors are
inserted in series with the leads from the sense resistor.
With the addition of R3, a current is generated through R1
causing an offset of:
V
OFFSET
= V
OUT
)
)
R1
R1 + R3
If V
OFFSET
> 0.025V, the minimum threshold will be
cancelled and Burst Mode operation is prevented from
occurring. Since V
OFFSET
is constant, the maximum load
current is also decreased by the same offset. Thus, to get
back to the same I
MAX
, the value of the sense resistor must
be reduced:
R
SENSE
m
75
I
MAX
To prevent noise spikes from erroneously tripping the
current comparator, a 1000pF capacitor is needed across
the SENSE
and SENSE
+
pins.
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1159. These items are also illustrated graphically in
the layout diagram of Figure 8. Check the following in your
layout:
4
3
21
LTC1159
SENSE
+
SENSE
9
8
1000pF
R1
100
R2
100
L
R
SENSE
C
OUT
R3
LTC1159 • F07
+
Figure 7. Suppressing Burst Mode Operation
4
3
2
1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P-GATE
V
IN
V
CC
P-DRIVE
V
CC
C
T
I
TH
SENSE
CAP
SHDN2
EXTV
CC
N-GATE
PGND
SGND
SENSE
+
C
OUT
D1
P-CHANNEL
1k
3300pFC
T
R1
R2
R
SENSE
N-CHANNEL
C
IN
L
+
+
V
OUT
V
IN
OUTPUT DIVIDER
REQUIRED WITH
ADJUSTABLE
VERSION ONLY
BOLD LINES INDICATE HIGH CURRENT PATHS
LTC1159 • F08
1000pF
100pF
1µF
0.15µF
1N4148
SHUTDOWN
5V EXTV
CC
CONNECTION
0.1 µF
V
FB
(SHDN1)
+
+
+
Figure 8. LTC1159 Layout Diagram (N and S Packages)
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LTC1159
LTC1159-3.3/LTC1159-5
1) Are the signal and power grounds segregated? The
LTC1159 signal ground must connect separately to the
(–) plate of C
OUT
. The other ground pin(s) should return to
the source of the N-channel MOSFET, anode of the Schot-
tky diode and (–) plate of C
IN
, which should have as short
lead lengths as possible.
2) Does the LTC1159 SENSE
pin connect to a point close
to R
SENSE
and the (+) plate of C
OUT
? In adjustable applica-
tions, the resistive divider R1, R2 must be connected
between the (+) plate of C
OUT
and signal ground.
3
) Are the SENSE
and SENSE
+
leads routed together
with minimum PC trace spacing? The differential
decoupling capacitor between the two SENSE pins should
be as close as possible to the LTC1159. Up to 100 may
be placed in series with each sense lead to help decouple
the SENSE pins. However, when these resistors are used,
the capacitor should be no larger than 1000pF.
4) Does the (+) plate of C
IN
connect to the source of the
P-channel MOSFET as closely as possible? An additional
0.1µF ceramic capacitor between V
IN
and power ground
may be required in some applications.
5) Is the V
CC
decoupling capacitor connected closely be-
tween the V
CC
pins of the LTC1159 and power ground?
This capacitor carries the MOSFET driver peak currents.
6) In adjustable versions, the feedback pin is very sensitive
to pickup from the switch node. Care must be taken to
isolate V
FB
from possible capacitive coupling of the induc-
tor switch signal.
7) Is the SHDN1 pin actively pulled to ground during
normal operation? SHDN1 is a high impedance pin and
must not be allowed to float.
Troubleshooting Hints
Since efficiency is critical to LTC1159 applications it is very
important to verify that the circuit is functioning correctly
in both continuous and Burst Mode operation. The wave-
form to monitor is the voltage on the C
T
pin .
In continuous mode (I
LOAD
> I
BURST
) the voltage should be
a sawtooth with a 0.9V
P-P
swing. This voltage should never
dip below 2V as shown in Figure 9a. When the load current
is low (I
LOAD
< I
BURST
), Burst Mode operation should occur
with the C
T
waveform periodically falling to ground as
shown in Figure 9b.
If the C
T
pin is observed falling to ground at high output
currents, it indicates poor decoupling or improper ground-
ing. Refer to the Board Layout Checklist.
3.3V
0V
(a) CONTINUOUS MODE OPERATION
3.3V
0V
(b) Burst Mode OPERATION
LTC1159 • F09
Figure 9. C
T
Pin 6 Waveforms
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LTC1159CS-3.3#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 3.3V Hi Eff Syn Stepdn Sw Reg
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