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LTC1159CS-3.3#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
4
LTC1159
LTC1159-3.3/LTC1159-5
Load Regulation
Efficiency vs Input Voltage
Line Regulation
Operating Frequency
vs (V
IN
– V
OUT
)
EXTV
CC
Pin Current
V
IN
Pin Current
INPUT VOLTAGE (V)
0
80
EFFICIENCY (%)
85
90
95
100
5101520
LTC1159 • TPC01
25 30 35 40
FIGURE 1 CIRCUIT
I
LOAD
= 1A
NOTE 6
INPUT VOLTAGE (V)
0
–60
∆V
OUT
(mV)
–40
–20
0
20
10 20
30
40
LT1159 • TPC02
40
60
515
25
35
FIGURE 1 CIRCUIT
I
LOAD
= 1A
NOTE 6
LOAD CURRENT (A)
0
–100
∆V
OUT
(mV)
–80
–60
–40
–20
0
20
0.5 1.0 1.5 2.0
LTC1159 • TPC03
2.5
FIGURE 1 CIRCUIT
V
IN
= 24V
INPUT VOLTAGE (V)
0
EXTV
CC
CURRENT (mA)
6
8
10
15 25 40
LTC1159 • TPC04
4
2
0
510
20
30 35
FIGURE 1 CIRCUIT
NOTE 6
I
LOAD
= 1A
I
LOAD
= 100mA
I
LOAD
= 0
INPUT VOLTAGE (V)
0
SUPPLY CURRENT (µA)
300
400
500
15 25 40
LTC1159 • TPC05
200
100
0
510
20
30 35
FIGURE 1 CIRCUIT
NOTE 6
NORMAL
V
SHDN2
= 2V
(V
IN
– V
OUT
) VOLTAGE (V)
0
NORMALIZED FREQUENCY
1.0
1.5
20
LTC1159 • TPC06
0.5
0
5
10
15
25
2.0
V
OUT
= 5V
T = 70°C
T = 0°C
T = 25°C
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Note 6: The LTC1159C, LTC1159C-3.3, and LTC1159C-5 are not tested
and not quality assurance sampled at –40°C and 85°C. These
specifications are guaranteed by design and/or correlation. The LTC1159I,
LTC1159I-3.3 and LTC1159I-5 are guaranteed and tested over the –40°C
to 85°C operating temperature range.
E
LECTR
IC
AL C CHARA TERIST
ICS
Note 7: The logic-level power MOSFETs shown in Figure 1 are rated for
V
DS(MAX)
= 30V. For operation at V
IN
> 30V, use standard threshold
MOSFETs with EXTV
CC
powered from a 12V supply. See Applications
Information.
5
LTC1159
LTC1159-3.3/LTC1159-5
PI FU CTIO S
U
UU
SENSE
+
: The (+) Input for the Current Comparator. A built-
in offset between the SENSE
+
and SENSE
–
pins, in conjunc-
tion with R
SENSE
, sets the current trip threshold.
N-Gate: High Current Drive for the Bottom N-Channel
MOSFET. The N-Gate pin swings from ground to V
CC
.
P-Gate: Level-Shifted Gate Drive Signal for the Top
P-Channel MOSFET. The voltage swing at the P-gate pin is
from V
IN
to V
IN
– V
CC
.
P-Drive: High Current Gate Drive for the Top P-Channel
MOSFET. The P-drive pin(s) swing(s) from V
CC
to ground.
CAP: Charge Compensation Pin. A capacitor to V
CC
pro-
vides charge required by the P-gate level-shift capacitor
during supply transitions.
The charge compensation ca-
pacitor must be larger than the gate drive capacitor
.
SHDN1: This pin shuts down the control circuitry only (V
CC
is not affected). Taking SHDN1 pin high turns off the
control circuitry and holds both MOSFETs off. This pin
must be at ground potential for normal operation.
SHDN2: Master Shutdown Pin. Taking SHDN2 high shuts
down V
CC
and all control circuitry.
V
IN
: Main Supply Input Pin.
SGND: Small-Signal Ground. Must be routed separately
from other grounds to the (–) terminal of C
OUT
.
PGND: Driver Power Grounds. Connect to source of N-
channel MOSFET and the (–) terminal of C
IN
.
V
CC
: Outputs of internal 4.5V linear regulator, EXTV
CC
switch, and supply inputs for driver and control circuits.
The driver and control circuits are powered from the higher
of the 4.5V regulator or EXTV
CC
voltage. Must be closely
decoupled to power ground.
C
T
: External capacitor C
T
from this pin to ground sets the
operating frequency. (The frequency is also dependent on
the ratio V
OUT
/V
IN
.)
I
TH
: Gain Amplifier Decoupling Point. The current com-
parator threshold increases with the I
TH
pin voltage.
V
FB
: For the LTC1159 adjustable version, the V
FB
pin
receives the feedback voltage from an external resistive
divider used to set the output voltage.
SENSE
–
: Connects to internal resistive divider which sets
the output voltage in fixed output versions. The SENSE
–
pin
is also the (–) input of the current comparator.
EXTV
CC
Switch Drop Current Sense Threshold Voltage
Off-Time vs V
OUT
SWITCH CURRENT (mA)
0
0
EXTV
CC
– V
CC
(mV)
100
200
300
400
500
600
5101520
LTC1159 • TPC07
OUTPUT VOLTAGE (V)
1
OFF-TIME (µs)
40
50
60
5
LTC1159 • TPC08
30
20
0
2
34
10
80
70
0
LTC1159-5
LTC1159-3.3
TEMPERATURE (°C)
20
SENSE VOLTAGE (mV)
80
100
120
100
LTC1159 • TPC09
60
40
0
40
60 80
20
160
140
0
MAXIMUM
THRESHOLD
MINIMUM
THRESHOLD
TYPICAL PERFOR A CE CHARACTERISTICS
UW
6
LTC1159
LTC1159-3.3/LTC1159-5
Internal divider broken at V
FB
for adjustable versions.
–
+
N-GATE
P-DRIVE
V
CC
550k
P-GATE
PGND
550k
CAP
LOW DROP SWITCH
V
CC
EXTV
CC
SHDN2
V
IN
–
+
–
+
SENSE
+
V
R
S
Q
V
TH1
–
+
25mV TO 150mV
13k
G
REFERENCE
1.25V
SGND
I
TH
C
V
OS
SENSE
–
LTC1159 • FD
SHDN1
–
+
T
V
TH2
S
SLEEP
C
T
V
FB
OFF-TIME
CONTROL
SENSE
–
LOW DROPOUT
4.5V REGULATOR
100k
FU CTIO AL DIAGRA
U
U
W
The LTC1159 uses a current mode, constant off-time
architecture to synchronously switch an external pair of
complementary power MOSFETs. Operating frequency is
set by an external capacitor at the C
T
pin.
The output voltage is sensed either by an internal voltage
divider connected to the SENSE
–
pin (LTC1159-3.3 and
LTC1159-5) or an external divider returned to the V
FB
pin
(LTC1159). A voltage comparator V, and a gain block G,
compare the divided output voltage with a reference volt-
age of 1.25V. To optimize efficiency, the LTC1159 auto-
matically switches between two modes of operation, burst
and continuous.
A low dropout 4.5V regulator provides the operating volt-
age V
CC
for the MOSFET drivers and control circuitry during
start-up. During normal operation, the LTC1159 family
powers the drivers and control from the output via the
EXTV
CC
pin to improve efficiency. The N-GATE pin is
referenced to ground and drives the N-channel MOSFET
gate directly. The P-channel gate drive must be referenced
to the main supply input V
IN
, which is accomplished by
level-shifting the P-drive signal via an internal 550k resistor
and external capacitor.
During the switch “ON” cycle in continuous mode, current
comparator C monitors the voltage between the SENSE
+
and SENSE
–
pins connected across an external shunt in
series with the inductor. When the voltage across the shunt
reaches its threshold value, the P-gate output is switched
to V
IN
, turning off the P-channel MOSFET. The timing
capacitor C
T
is now allowed to discharge at a rate deter-
mined by the off-time controller. The discharge current is
made proportional to the output voltage to model the
inductor current, which decays at a rate which is also
proportional to the output voltage. While the timing
capacitor is discharging, the N-gate output is high, turning
on the N-channel MOSFET.
When the voltage on C
T
has discharged past V
TH1
, compara-
tor T trips, setting the flip-flop. This causes the N-gate output
to go low (turning off the N-channel MOSFET) and the P-
gate output to also go low (turning the P-channel MOSFET
back on). The cycle then repeats. As the load current
(Refer to Functional Diagram)
OPERATIO
U
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LTC1159CS-3.3#PBF

Mfr. #:
Buy LTC1159CS-3.3#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 3.3V Hi Eff Syn Stepdn Sw Reg
Lifecycle:
New from this manufacturer.
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