ISL9001AIRBZ-T

10
FN6433.3
December 10, 2015
LDO Regulation and Programmable Output Divider
The LDO Regulator is implemented with a high-gain
operational amplifier driving a PMOS pass transistor. The
design of the ISL9001A provides a regulator that has low
quiescent current, fast transient response, and overall
stability across all operating and load current conditions.
LDO stability is guaranteed for a 1µF to 10µF output
capacitor that has a tolerance better than 20% and ESR less
than 200m. The design is performance-optimized for a 1µF
capacitor. Unless limited by the application, use of an output
capacitor value above 4.7µF is not recommended as LDO
performance improvement is minimal.
Soft-start circuitry integrated into each LDO limits the initial
ramp-up rate to about 30µs/V to minimize current surge. The
ISL9001A provides short-circuit protection by limiting the
output current to about 425mA.
The LDO uses an independently trimmed 1V reference as its
input. An internal resistor divider drops the LDO output
voltage down to 1V. This is compared to the 1V reference for
regulation. The resistor division ratio is programmed in the
factory.
Power-On Reset Generation
The ISL9001A has a Power-on Reset signal generation
circuit, which indicates that output power is good. The POR
signal is generated as follows.
A POR comparator continuously monitors the output of the
LDO. The LDO enters a power-good state when the output
voltage is above 94% of the expected output voltage for a
period exceeding the LDO PGOOD entry delay time (see the
following). In the power-good state, the open-drain POR
output is in a high-impedance state. An internal 100k
pull-up resistor pulls the pin up to the LDO output voltage. An
external resistor can be added between the POR
output and
the LDO output for a faster rise time, however, the POR
output should not connect through an external resistor to a
supply greater than the LDO voltage.
The power-good state is exited when the LDO output falls
below 90% of the expected output voltage for a period longer
than the PGOOD exit delay time. While power-good is false,
the ISL9001A pulls the POR pin low.
The PGOOD entry and exit delays are determined by the
value of an external capacitor connected to the CPOR pin.
For a 0.01µF capacitor, the entry and exit delays are 200ms
and 25µs respectively. Larger or smaller capacitor values will
yield proportionately longer or shorter delay times. The POR
exit delay should never be allowed to be less than 10µs to
ensure sufficient immunity against transient induced false
POR triggering.
Overheat Detection
The bandgap outputs a proportional-to-temperature current
that is indicative of the temperature of the silicon. This
current is compared with references to determine if the
device is in danger of damage due to overheating. When the
die temperature reaches about +140°C, if the LDO is
sourcing more than 50mA, it shuts down until the die cools
sufficiently. Once the die temperature falls back below about
+110°C, the disabled LDO is re-enabled and soft-start
automatically takes place.
ISL9001A
11
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FN6433.3
December 10, 2015
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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Reliability reports are also available from our website at www.intersil.com/support
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE REVISION CHANGE
December 10, 2015 FN6433.3 Added Rev History and About Intersil Verbiage.
Updated Ordering Information on page 2
Updated POD L8.2x3 to most current version. Rev changes are as follows:
Tiebar Note 5 updated
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or
ends).
Bottom View:
Changed exposed pad height from 1.80 +/-0.10 to 1.80 +0.10/-0.15
Changed exposed pad width from 1.65 +/-0.10 to 1.65 +0.10/-0.15
Side View:
Changed 0.05 to 0.05 MAX
Converted to new POD standards by adding land pattern and moving dimensions from table onto drawing.
ISL9001A
12
FN6433.3
December 10, 2015
ISL9001A
Package Outline Drawing
L8.2x3
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 3/15
located within the zone indicated. The pin #1 identifier may be
Unless otherwise specified, tolerance : Decimal ± 0.05
The configuration of the pin #1 identifier is optional, but must be
between 0.25mm and 0.30mm from the terminal tip.
Dimension applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
BOTTOM VIEW
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
Compies to JEDEC MO-229 VCED-2.7.
(4X) 0.15
INDEX AREA
PIN 1
PIN #1
C
SEATING PLANE
BASE PLANE
0.08
SEE DETAIL "X"
C
C
4
6
A
B
0.90 ±0.10
0.05 MAX
0.05 MAX
0.20 REF
2.00
3.00
2X 1.50
8X 0.40 ±0.10
8X 0.25 +0.07/-0.05
INDEX AREA
6X 0.50
(1.65)
(1.50)
(8X 0.60)
(8X 0.25)
(1.80)
(2.80)
(6X 0.50)
1
8
0.10 AMC B
0.10 C
1.80 +0.10/-0.15
1.65 +0.10/-0.15
either a mold or mark feature.
Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).

ISL9001AIRBZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
LDO Voltage Regulators W/ANNEAL SINGLELDO LW IQ HI PSRR 1 5V
Lifecycle:
New from this manufacturer.
Delivery:
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