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NB4N840MMNTWG

P1-P3P4-P6P7-P9
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 5
1
Publication Order Number:
NB4N840M/D
NB4N840M
3.3V 3.2Gb/s Dual
Differential Clock/Data 2 x 2
Crosspoint Switch with
CML Output and Internal
Termination
Description
The NB4N840M is a high−bandwidth fully differential dual
2 x 2 crosspoint switch with CML inputs/outputs that is suitable for
applications such as SDH/SONET, DWDM, Gigabit Ethernet and
high speed switching. Fully differential design techniques are used to
minimize jitter accumulation, crosstalk, and signal skew, which make
this device ideal for loop−through and protection channel switching
applications.
Internally terminated differential CML inputs accept AC−coupled
LVPECL (Positive ECL) or direct coupled CML signals. By providing
internal 50 W input and output termination resistor, the need for
external components is eliminated and interface reflections are
minimized. Differential 16 mA CML outputs provide matching
internal 50 W terminations, and 400 mV output swings when
externally terminated, 50 W to V
CC
.
Single−ended LVCMOS/LVTTL SEL inputs control the routing of
the signals through the crosspoint switch which makes this device
configurable as 1:2 fan−out, repeater or 2 x 2 crosspoint switch. The
device is housed in a low profile 5 x 5 mm 32−pin QFN package.
Features
• Plug−in compatible to the MAX3840 and SY55859L
• Maximum Input Clock Frequency 2.7 GHz
• Maximum Input Data Frequency 3.2 Gb/s
• 225 ps Typical Propagation Delay
• 80 ps Typical Rise and Fall Times
• 7 ps Channel to Channel Skew
• 430 mW Power Consumption
• < 0.5 ps RMS Jitter
• 7 ps Peak−to−Peak Data Dependent Jitter
• Power Saving Feature with Disabled Outputs
• Operating Range: V
CC
= 3.0 V to 3.6 V with V
EE
= 0 V
• CML Output Level (400 mV Peak−to−Peak Output), Differential
Output
• These are Pb−Free Devices
QFN32
MN SUFFIX
CASE 488AM
See detailed ordering and shipping information on page 8 o
f
this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAM
http://onsemi.com
32
1
NB4N
840M
ALYWG
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
CML
CML
CML
CML
CML
CML
CML
CML
0
1
0
1
0
1
0
1
Figure 1. Functional Block Diagram
QA0
QA0
ENA0
SELA0
QA1
QA1
ENA1
SELA1
QB0
QB0
ENB0
SELB0
QB1
QB1
ENB1
SELB1
DA0
DA0
DA1
DA1
DB0
DB0
DB1
DB1
NB4N840M
http://onsemi.com
2
Table 1. TRUTH TABLE
SELA0/SELB0 SELA1/SELB1 ENA0/ENA1 ENB0/ENB1 QA0/QB0 QA1/QB1 Function
L L H H DA0/DB0 DA0/DB0 1:2 Fanout
L H H H DA0/DB0 DA1/DB1 Quad Repeater
H L H H DA1/DB1 DA0/DB0 Crosspoint Switch
H H H H DA1/DB1 DA1/DB1 1:2 Fanout
X X L L Disable/Power Down Disable/Power Down No output (@ V
CC
)
Figure 2. Pin Configuration (Top View)
32 31 30 29 28 27 26 25
9 10 11121314 1516
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
ENB1
SELB1
DB1
DB1
DB0
ENB0
SELB0
DB0
GND
V
CC
QA0
QA1
QA1
V
CC
QA0
V
CC
GND
V
CC
V
CC
QB0
QB0
QB1
QB1
V
CC
ENA1
DA1
DA1
DA0
DA0
ENA0
SELA0
SELA1
NB4N840M
NB4N840M
http://onsemi.com
3
Table 2. PIN DESCRIPTION
Pin Name I/O Description
1 ENB1 LVTTL Channel B1 Output Enable. LVTTL low input powers down B1 output stage.
2 DB1 CML Input Channel B1 Positive Signal Input
3 DB1 CML Input Channel B1 Negative Signal Input
4 ENB0 LVTTL Channel B0 Output Enable. LVTTL low input powers down B0 output stage.
5 SELB0 LVTTL Channel B0 Output Select. See Table 1.
6 DB0 CML Input Channel B0 Positive Signal Input
7 DB0 CML Input Channel B0 Negative Signal Input
8 SELB1 LVTTL Channel B1 Output Select. See Table 1.
9,24 GND − Supply Ground. All GND pins must be externally connected to power supply to guarantee
proper operation.
10, 13, 16,
17, 20, 23
V
CC
− Positive Supply. All V
CC
pins must be externally connected to power supply to guarantee
proper operation.
11 QB0 CML Output Channel B0 Negative Output.
12 QB0 CML Output Channel B0 Positive Output.
14 QB1 CML Output Channel B1 Negative Output.
15 QB1 CML Output Channel B1 Positive Output.
18 QA1 CML Output Channel A1 Negative Output.
19 QA1 CML Output Channel A1 Positive Output.
21 QA0 CML Output Channel A0 Negative Output.
22 QA0 CML Output Channel A0 Positive Output.
25 SELA1 LVTTL Channel A1 Output Select, LVTTL Input. See Table 1.
26 DA0 CML Input Channel A0 Positive Signal Input.
27 DA0 CML Input Channel A0 Negative Signal Input.
28 SELA0 LVTTL Channel A0 Output Select, LVTTL Input. See Table 1.
29 ENA0 LVTTL Channel A0 Output Enable. LVTTL low input powers down A0 output stage.
30 DA1 CML Input Channel A1 Positive Signal Input.
31 DA1 CML Input Channel A1 Negative Signal Input.
32 ENA1 LVTTL Channel A1 Output Enable. LVTTL low input powers down A1 output stage.
− EP GND Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing)
must be attached to a heat−sinking conduit. The exposed pad must be soldered to the
circuit board GND for proper electrical and thermal operation.
P1-P3P4-P6P7-P9

NB4N840MMNTWG

Mfr. #:
Buy NB4N840MMNTWG
Manufacturer:
ON Semiconductor
Description:
Analog & Digital Crosspoint ICs DUAL DIFF 2X2 SWITCH
Lifecycle:
New from this manufacturer.
Delivery:
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