NB4N840M
http://onsemi.com
5
Table 5. DC CHARACTERISTICS, CLOCK INPUTS, CML OUTPUTS V
CC
= 3.0 V to 3.6 V, T
A
= −40°C to +85°C
Symbol
Characteristic Min Typ Max Unit
I
CC
Power Supply Current (All outputs enabled) 130 170 mA
Vout
diff
CML Differential Output Swing (Note 4, Figures 5 and 12) 640 800 1000 mV
V
CMR
(Note 6)
CML Output Common Mode Voltage (Loaded 50 W to V
CC
)
V
CC
− 200 mV
CML Single−Ended Input Voltage Range V
CC
− 800 V
CC
+ 400 mV
V
ID
Differential Input Voltage (V
IHD
− V
ILD
) 300 1600 mV
LVTTL CONTROL INPUT PINS
V
IH
Input HIGH Voltage (LVTTL Inputs) 2000 mV
V
IL
Input LOW Voltage (LVTTL Inputs) 800 mV
I
IH
Input HIGH Current (LVTTL Inputs) −10 10
mA
I
IL
Input LOW Current (LVTTL Inputs) −10 10
mA
R
TIN
CML Single−Ended Input Resistance 42.5 50 57.5
W
R
TOUT
Differential Output Resistance 85 100 115
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. CML outputs require 50 W receiver termination resistors to V
CC
for proper operation (Figure 10).
5. Input and output parameters vary 1:1 with V
CC
.
6. V
CMR
min varies 1:1 with V
EE
, V
CMR
max varies 1:1 with V
CC
.
Table 6. AC CHARACTERISTICS V
CC
= 3.0 V to 3.6 V, V
EE
= 0 V (Note 7, Figure 9)
Symbo
Characteristic
−40°C 25°C 85°C
Uni
Min Typ Max Min Typ Max Min Typ Max
V
OUTPP
Output Voltage Amplitude (@ V
INPPmin
)f
in
≤ 2 GHz
(See Figure 3) f
in
≤ 3 GHz
f
in
≤ 3.5 GHz
280
235
170
365
310
220
280
235
170
365
310
220
280
235
170
365
310
220
mV
f
DATA
Maximum Operating Data Rate 3.2 3.2 3.2 Gb/s
t
PLH
,
t
PHL
Propagation Delay to Output Differential
D/D to Q/Q 140 225 340 140 225 340 140 225 340
ps
t
SKEW
Duty Cycle Skew (Note 8)
Within−Device Skew (Figure 4)
Device−to−Device Skew (Note 12)
5
5
20
25
25
85
5
5
20
25
25
85
5
5
20
25
25
85
ps
t
JITTER
RMS Random Clock Jitter (Note 10) f
in
v 3.2 GHz
Peak−to−Peak Data Dependent Jitter f
in
= 2.5 Gb/s
(Note 11) f
in
= 3.2 Gb/s
0.15
7
7
0.5
20
20
0.15
7
7
0.5
20
20
0.15
7
7
0.5
20
20
ps
Crosstalk−Induced RMS Jitter (Note 13) 0.5 0.5 0.5 ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 9)
150 800 150 800 150 800 mV
t
r
t
f
Output Rise/Fall Times @ 0.5 GHz Q, Q
(20% − 80%)
80 135 80 135 80 135 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Measured by forcing V
INPP
(MIN) from a 50% duty cycle clock source. All loading with an external R
L
= 50 W to V
CC
. Input edge rates 40 ps
(20% − 80%).
8. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5 GHz.
9. V
INPP
(MAX) cannot exceed 800 mV. Input voltage swing is a single−ended measurement operating in differential mode.
10.Additive RMS jitter using 50% duty cycle clock input signal.
11. Additive peak−to−peak data dependent jitter using input data pattern with PRBS 2
23
−1 and K28.5, V
INPP
= 400 mV.
12.Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
13.Data taken on the same device under identical condition.
