LTC1840
9
1840f
DIV1 and DIV0 program the ratio by which the internal
50kHz oscillator frequency is divided down to produce the
tachometer clocks (2, 4, 8, or 16). The DIV bits power-up
low, which corresponds to a frequency division of 16. For
example, if DIV1 and DIV0 are both high, the divide ratio
is set to 2. If DIV1 is high and DIV0 is low, the divide ratio
is set to 4. If DIV1 is low and DIV0 is high, the divide ratio
is set to 8.
The TACHA and TACHB registers will be set to all ones
by a UVLO condition. The tach counters count between
rising edges on the TACHA and TACHB pins. If a counter
overflows its maximum count of 255, the latch holding the
count results is immediately set to 255 without waiting for
the next edge on its TACH pin. This is done so that a
suddenly stopped or locked rotor will be easily detectable
by reading its corresponding tach register; otherwise, the
register would merely hold the previous count and be
waiting for a tach signal edge that isn’t coming to update
the overflow count.
The GPIOX pin bits in the GPIO data register reflect the
logic state of the pin itself, while the GPIOX register bits
reflect the data that is stored in the register that controls
the gate of the internal pull-down for the pin. The logic
polarities of the GPIOX bits are the same as those of the
GPIOX pins assuming an appropriately sized pull-up resis-
tor (for example, a 1 value for the GPIO1 register bit will
force the internal N-channel MOSFET pull-down to an off-
state, resulting in a 1 value at the GPIO1 pin). For a GPIO
to be used as a digital input, the GPIOX register bit is set
high, which turns off the internal pull-down N-channel
MOSFET, and the state of the pin can be controlled
externally and read back via the GPIOX pin bit. The GPIO
register bits power-up in the high state.
The GPIOX BLNK bits in the GPIO setup register control
whether the internal pull-down on a GPIO shuts on and off
at about 1.5Hz when the GPIOX register bit is low, and the
GPIOX FLTEN bits control whether a GPIO pin can trigger
a fault condition by a change in state. The GPIO FLTEN and
GPIO BLNK bits power-up in the low state.
Serial Interface Example
In this example, an LTC1840 has both address pins open
(NC) and the output current of DACA will be programmed
to half of full-scale (50µA current sink).
Provide a start condition on the bus by pulling SDA from
high to low while SCL is high and then write the SDA bit
stream 1110010 to the part for the LTC1840 slave
address, followed by a 0 to indicate that a write operation
will follow. All SDA transitions must happen when SCL is
low, or a start or stop condition will be interpreted. The
LTC1840 will then pull the SDA line low during the next
SCL clock phase to indicate that it is responding to the
communication attempt. To write to the DACA output
register, write 00000010 to the LTC1840 and wait for the
LTC1840 to acknowledge again on the following SCL cycle
by pulling SDA low. Next, send the LTC1840 the value
indicating the DACA current; writing the SDA data stream
10000000 sets the DAC to sink 50µA. The LTC1840 will
then acknowledge a third time by pulling SDA low for the
next SCL cycle. Then the data will be written into the
internal DACA register and I
DACOUTA
pin will sink 50µA.
Now generate a stop condition by forcing SDA from low to
high while SCL is high.
Tachometer Interface Operation
It is common for fans to have tachometer outputs that
produce two pulses per blade revolution. The LTC1840
provides two inputs that interface to circuits that count
between rising edges on these pulses. The frequency at
which the counting is done is programmable via the serial
interface to 25kHz, 12.5kHz, 6.25kHz, and 3.125kHz,
equivalent to divide by 2, 4, 8, and 16 operations on the
internal 50kHz oscillator. The count values corresponding
to these two inputs can also be read via the serial interface.
The output registers storing these counts power-up to all
ones, and they will also be loaded with all ones whenever
a counter overflows between two rising edges to allow for
the detection of a suddenly stopped rotor. The part can
also be configured to produce a fault as soon as the
counter overflows. However, the default state is to not
produce such faults, so as to prevent unnecessary fault
conditions while the fan is spinning up at start-up.
Multiple fans with open drain tachometer output signals
can be connected to a single LTC1840 tachometer input in
a wired-OR fashion, as long as the fans are not active at the
same time. If the fans happen to be spinning simulta-
neously, the counts in the tach registers will not be
meaningful.
OPERATIO
U
