5
HFBR-2528Z Receiver
The HFBR-2528Z receiver consists of a silicon PIN photodiode and digitizing
IC to produce a logic compatible output. The IC includes a unique circuit to
correct the pulse width distortion (PWD) of the rst bit after a long idle pe-
riod. This enables operation from DC to 10 MBd with low PWD for arbitrary
data patterns.
The receiver output is a “push-pull” stage compatible with TTL and CMOS
logic. The receiver housing is a dark, conductive plastic, compatible with all
Versatile Link connectors.
HFBR-2528Z Receiver, top view
Electrical and Optical Characteristics: T
A
=
-40° to +85°C, 4.75 V < V
CC
< 5.25 V, unless otherwise noted.
Parameter Symbol Min. Typ
.[1]
Max. Unit T
A
(°C) Condition Note Fig.
Peak POF Sensitivity: P
RL,min
-23.0 -21.0 dBm +25 1 mm POF, 2,6 8,10
Minimum Input for -20.0 0 to +70 |PWD| < 30 ns
Logic “0” -19.5 -40 to +85
Peak POF Overdrive P
RL,max
+1.0 +5.0 dBm +25 1 mm POF, 2,3, 7,8,
Limit:Maximum +0.0 0 to +70 |PWD| < 30 ns 6 9
Input for Logic “0” -1.0 -40 to +85
Peak POF O State P
RH,max
-42 dBm 1 mm POF 2,6,
Limit: Maximum 8
Input for Logic “1”
Peak HCS P
RL,min
-25.0 -23.0 dBm +25 200 μm HCS
, 2,6
Sensitivity: Minimum -22.0 0 to +70 |PWD| < 30 ns
Input for Logic “0” -21.5 -40 to +85
Peak HCS Overdrive P
RL,max
-1.0 +3.0 dBm +25 200 μm HCS
, 2,3,
Limit: Maximum -2.0 0 to +70 |PWD| < 30 ns 6
Input for Logic “0” -3.0 -40 to +85
Peak HCS O State P
RH,max
-44 dBm 200 μm HCS
2,6,
Limit: Maximum 8
Input for Logic “1”
Supply Current I
CC
19 45 mA V
O
= Open
High Level Output V
OH
4.2 4.7 V I
O
= -40 μA
Voltage
Low Level Output V
OL
0.22 0.4 V I
O
= +1.6 mA
Voltage
Output Rise Time t
r
12 30 ns C
L
= 10 pF 6
Output Fall Time t
f
10 30 ns C
L
= 10 pF 6
Thermal Resistance,
jc
200 °C/W 4
Junction to Case
Electric Field E
MAX
8 V/m Near Field, 5
Immunity Electrical
Field Source
Power Supply PSNI 0.1 0.4 V
pp
Sine Wave 6
Noise Immunity DC - 10 MHz
Notes:
1. Typical data are at +25°C, V
CC
= 5.0 V.
2. Input power levels are for peak (not average) optical input levels. For 50% duty cycle data, peak optical power is twice the average optical
power.
3. Receiver overdrive (P
RL,max
) is speci ed as the limit where |PWD| will not exceed 30 ns. The receiver will be in the correct state (logic “0”) for opti-
cal powers above P
RL,max
. However, it may not meet a 30% symbol period PWD if the overdrive limit is exceeded. Refer to Figure 8 for PWD per-
formance at high received optical powers.
4. Typical value measured from junction to PC board solder joint for horizontal mount package, HFBR-2528Z.
5. Pins 5 and 8 are electrically connected to the conductive housing and are also used for mounting and retaining purposes. It is required that
pins 5 and 8 be connected to ground to maintain conductive housing shield e ectiveness.
6. In recommended receiver circuit, with an optical signal from the recommended transmitter circuit.
7. Pin 4 is electrically isolated internally. Pin 4 may be externally connected to pin 1 for board layout compatibility with HFBR-25X1Z, HFBR-25X2Z
and HFBR-25X4Z. Otherwise it is recommended pin 4 be grounded as in Figure 11.
8. BER ≤ 10E-9, includes a 10.8 dB margin below the receiver switching threshold level (signal to noise ratio = 12).
NO CONNECT
4
V
CC
3
GROUND
2
V
O
1
GROUND 5
GROUND 8
SEE NOTES 5,7
IC
