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ADV7125KSTZ140

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
Data Sheet ADV7125
Rev. D | Page 3 of 17
SPECIFICATIONS
5 V ELECTRICAL CHARACTERISTICS
V
AA
= 5 V ± 5%, V
REF
= 1.235 V, R
SET
= 560 Ω, C
L
= 10 pF. All specifications T
MIN
to T
MAX
,
1
unless otherwise noted, T
J MAX
= 110°C.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
1
STATIC PERFORMANCE
Resolution (Each DAC) 8 Bits
Integral Nonlinearity (BSL) −1 ±0.4 +1 LSB
Differential Nonlinearity
±0.25
LSB
Guaranteed Monotonic
DIGITAL AND CONTROL INPUTS
Input High Voltage, V
IH
2 V
Input Low Voltage, V
IL
0.8 V
Input Current, I
IN
−1 +1 μA V
IN
= 0.0 V or V
DD
PSAVE Pull-Up Current
20 μA
Input Capacitance, C
IN
10 pF
ANALOG OUTPUTS
Output Current 2.0 26.5 mA
Green DAC,
SYNC = high
2.0 18.5 mA
RGB DAC,
SYNC = low
DAC-to-DAC Matching 1.0 5 %
Output Compliance Range, V
OC
0 1.4 V
Output Impedance, R
OUT
100 kΩ
Output Capacitance, C
OUT
10 pF I
OUT
= 0 mA
Offset Error −0.025 +0.025 % FSR Tested with DAC output = 0 V
Gain Error
2
−5.0 +5.0 % FSR FSR = 18.62 mA
VOLTAGE REFERENCE, EXTERNAL AND
INTERNAL
Reference Range, V
REF
1.12 1.235 1.35 V
POWER DISSIPATION
Digital Supply Current
3
3.4 9 mA f
CLK
= 50 MHz
10.5 15 mA f
CLK
= 140 MHz
18 25 mA f
CLK
= 240 MHz
Analog Supply Current 67 72 mA R
SET
= 530 Ω
8 mA R
SET
= 4933 Ω
Standby Supply Current
4
2.1
mA
PSAVE = low, digital, and control inputs at V
DD
Power Supply Rejection Ratio 0.1 0.5 %/%
1
Temperature range T
MIN
to T
MAX
: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.
2
Gain error = ((Measured (FSC)/Ideal (FSC) − 1) × 100), where Ideal = V
REF
/R
SET
× K × (0xFFH) × 4 and K = 7.9896.
3
Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and V
DD
.
4
These maximum/minimum specifications are guaranteed by characterization in the 4.75 V to 5.25 V range.
ADV7125 Data Sheet
Rev. D | Page 4 of 17
3.3 V ELECTRICAL CHARACTERISTICS
V
AA
= 3.0 V to 3.6 V, V
REF
= 1.235 V, R
SET
= 560 Ω, C
L
= 10 pF. All specifications T
MIN
to T
MAX
,
1
unless otherwise noted, T
J MAX
= 110°C.
Table 2.
Parameter
2
Min Typ Max Unit Test Conditions/Comments
1
STATIC PERFORMANCE
Resolution (Each DAC) 8 Bits R
SET
= 680 Ω
Integral Nonlinearity (BSL) −1 ±0.5 +1 LSB R
SET
= 680 Ω
Differential Nonlinearity −1 ±0.25 +1 LSB R
SET
= 680 Ω
DIGITAL AND CONTROL INPUTS
Input High Voltage, V
IH
2.0 V
Input Low Voltage, V
IL
0.8 V
Input Current, I
IN
−1 +1 μA V
IN
= 0.0 V or V
DD
PSAVE Pull-Up Current
20 μA
Input Capacitance, C
IN
10 pF
ANALOG OUTPUTS
Output Current 2.0 26.5 mA
Green DAC,
SYNC = high
2.0 18.5 mA
RGB DAC,
SYNC = low
DAC-to-DAC Matching 1.0 %
Output Compliance Range, V
OC
0 1.4 V
Output Impedance, R
OUT
70 kΩ
Output Capacitance, C
OUT
10
pF
Offset Error 0 0 % FSR Tested with DAC output = 0 V
Gain Error
3
0 % FSR FSR = 18.62 mA
VOLTAGE REFERENCE, EXTERNAL
Reference Range, V
REF
1.12 1.235 1.35 V
VOLTAGE REFERENCE, INTERNAL
Voltage Reference, V
REF
1.235 V
POWER DISSIPATION
Digital Supply Current
4
2.2
5.0
mA
f
CLK
= 50 MHz
6.5 12.0 mA f
CLK
= 140 MHz
11 15 mA f
CLK
= 240 MHz
16 mA f
CLK
= 330 MHz
Analog Supply Current 67 72 mA R
SET
= 560 Ω
8 mA R
SET
= 4933 Ω
Standby Supply Current
2.1
5.0
mA
PSAVE = low, digital, and control inputs at V
DD
Power Supply Rejection Ratio 0.1 0.5 %/%
1
Temperature range T
MIN
to T
MAX
: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.
2
These max/min specifications are guaranteed by characterization in the 3.0 V to 3.6 V range.
3
Gain error = ((Measured (FSC)/Ideal (FSC) −1) × 100), where Ideal = V
REF
/R
SET
× K × (0xFFH) × 4 and K = 7.9896.
4
Digital supply is measured with continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and V
DD
.
Data Sheet ADV7125
Rev. D | Page 5 of 17
5 V TIMING SPECIFICATIONS
V
AA
= 5 V ± 5%,
1
V
REF
= 1.235 V, R
SET
= 560 Ω, C
L
= 10 pF. All specifications T
MIN
to T
MAX
,
2
unless otherwise noted, T
J MAX
= 110°C.
Table 3.
Parameter
3
Symbol Min Typ Max Unit Test Conditions/Comments
ANALOG OUTPUTS
Analog Output Delay t
6
5.5 ns
Analog Output Rise/Fall Time
4
t
7
1.0 ns
Analog Output Transition Time
5
t
8
15 ns
Analog Output Skew
6
t
9
1 2 ns
CLOCK CONTROL
CLOCK Frequency
7
f
CLK
0.5 50 MHz 50 MHz grade
0.5 140 MHz 140 MHz grade
0.5 240 MHz 240 MHz grade
Data and Control Setup
6
t
1
0.5 ns
Data and Control Hold
6
t
2
1.5 ns
CLOCK Period t
3
4.17 ns
CLOCK Pulse Width High
6
t
4
1.875 ns f
CLK_MAX
= 240 MHz
CLOCK Pulse Width Low
6
t
5
1.875 ns f
CLK_MAX
= 240 MHz
CLOCK Pulse Width High
6
t
4
2.85 ns f
CLK_MAX
= 140 MHz
CLOCK Pulse Width Low
6
t
5
2.85 ns f
CLK_MAX
= 140 MHz
CLOCK Pulse Width High
t
4
8.0
ns
f
CLK_MAX
= 50 MHz
CLOCK Pulse Width Low t
5
8.0 ns f
CLK_MAX
= 50 MHz
Pipeline Delay
6
t
PD
1.0 1.0 1.0 Clock cycles
PSAVE Up Time
6
t
10
2 10
ns
1
The maximum and minimum specifications are guaranteed over this range.
2
Temperature range T
MIN
to T
MAX
: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.
3
Timing specifications are measured with input levels of 3.0 V (V
IH
) and 0 V (V
IL
) for both 5 V and 3.3 V supplies.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
f
CLK
maximum specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

ADV7125KSTZ140

Mfr. #:
Buy ADV7125KSTZ140
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 330MHz Triple 8B High Speed DAC
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