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ADV7125KSTZ140

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
ADV7125 Data Sheet
Rev. D | Page 6 of 17
3.3 V TIMING SPECIFICATIONS
V
AA
= 3.0 V to 3.6 V,
1
V
REF
= 1.235 V, R
SET
= 560 Ω, C
L
= 10 pF. All specifications T
MIN
to T
MAX
,
2
unless otherwise noted, T
J MAX
= 110°C.
Table 4.
Parameter
3
Symbol Min Typ Max Unit Test Conditions/Comments
ANALOG OUTPUTS
Analog Output Delay, t
6
7.5 ns
Analog Output Rise/Fall Time
4
t
7
1.0 ns
Analog Output Transition Time
5
t
8
15 ns
Analog Output Skew
6
t
9
1 2 ns
CLOCK CONTROL
CLOCK Frequency
7
f
CLK
50 MHz 50 MHz grade
140 MHz 140 MHz grade
240
MHz
240 MHz grade
330 MHz 330 MHz grade
Data and Control Setup
6
t
1
0.2 ns
Data and Control Hold
6
t
2
1.5 ns
CLOCK Period t
3
3 ns
CLOCK Pulse Width High
6
t
4
1.4 ns f
CLK_MAX
= 330 MHz
CLOCK Pulse Width Low
6
t
5
1.4 ns f
CLK_MAX
= 330 MHz
CLOCK Pulse Width High
6
t
4
1.875 ns f
CLK_MAX
= 240 MHz
CLOCK Pulse Width Low
6
t
5
1.875 ns f
CLK_MAX
= 240 MHz
CLOCK Pulse Width High
6
t
4
2.85 ns f
CLK_MAX
= 140 MHz
CLOCK Pulse Width Low
6
t
5
2.85 ns f
CLK_MAX
= 140 MHz
CLOCK Pulse Width High
t
4
8.0
ns
f
CLK_MAX
= 50 MHz
CLOCK Pulse Width Low t
5
8.0 ns f
CLK_MAX
= 50 MHz
Pipeline Delay
6
t
PD
1.0 1.0 1.0 Clock cycles
PSAVE Up Time
6
t
10
4 10
ns
1
These maximum and minimum specifications are guaranteed over this range.
2
Temperature range: T
MIN
to T
MAX
: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.
3
Timing specifications are measured with input levels of 3.0 V (V
IH
) and 0 V (V
IL
) for 3.3 V supplies.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
f
CLK
maximum specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.
t
3
t
1
t
4
t
8
t
2
t
6
t
7
t
5
CLOCK
DIGITAL INPUTS
(R7 TO R0, G7 TO G0, B7 TO B0,
SYNC, BLANK)
ANALOG OUTPUTS
(IOR, IOR, IOG, IOG, IOB, IOB)
NOTES
1. OUTPUT DELAY (
t
6
) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT
OF FULL-SCALE TRANSITION.
2. OUTPUT RISE/FALL TIME (
t
7
) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION.
3. TRANSITION TIME (
t
8
) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE
FINAL OUTPUT VALUE.
03097-002
Figure 2. Timing Diagram
Data Sheet ADV7125
Rev. D | Page 7 of 17
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
V
AA
to GND 7 V
Voltage on Any Digital Pin GND − 0.5 V to V
AA
+ 0.5 V
Ambient Operating Temperature
Range (T
A
)
−40°C to +85°C
Storage Temperature Range (T
S
) −65°C to +150°C
Junction Temperature (T
J
) 150°C
Lead Temperature (Soldering, 10 sec) 300°C
Vapor Phase Soldering (1 Minute)
220°C
I
OUT
to GND
1
0 V to V
AA
1
Analog output short circuit to any power supply or common GND can be of
an indefinite duration.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
ADV7125 Data Sheet
Rev. D | Page 8 of 17
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
13
14
15
16
17
18
19
20
21
22
23
24
V
AA
GND
GND
B0
B1
B2
B3
B4
B5
B6
B7
CLOCK
48
47
46
45
44
43
42
41
40
39
38
37
R7
R6
R5
R4
R3
R2
R1
R0
GND
GND
PSAVE
R
SET
1
2
3
4
5
6
7
8
9
10
11
12
GND
GND
G0
G1
G2
G3
G4
G5
G6
G7
BLANK
SYNC
NOTES
1. THE EXPOSED PADDLE MUST BE CONNECTED TO GND.
COMP
V
AA
V
AA
IOB
IOB
GND
GND
35
V
REF
36
34
33
32
31
30
29
28
27
26
25
T
O
P VIEW
(Not to Scale)
ADV7125
PIN 1
INDIC
A
TOR
03097-003
IOG
IOG
IOR
IOR
Figure 3. LFCSP Pin Configuration (CP-48-1)
V
AA
GND
GND
B0
B1
B2
B3
B4
B5
B6
B7
CLOCK
R7
R6
R5
R4
R3
R2
R1
R0
GND
GND
PSAVE
R
SET
GND
GND
G0
G1
G2
G3
G4
G5
G6
G7
BLANK
SYNC
NOTES
1. THE EXPOSED PADDLE MUST BE CONNECTED TO GND.
COMP
V
AA
V
AA
IOB
IOB
GND
GND
V
REF
IOG
IOG
IOR
IOR
1
2
3
4
5
6
7
24
23
22
21
20
19
18
17
16
15
14
13
44
45
46
47
48
43
42
41
40
39
38
37
ADV7125
TOP VIEW
(Not to Scale)
25
26
27
28
29
30
31
32
33
34
35
36
8
9
10
11
12
03097-100
Figure 4. LFCSP Pin Configuration (CP-48-4)
Table 6. LFCSP Pin Function Descriptions
Pin No. Mnemonic Description
1, 2, 14, 15,
25, 26, 39, 40
GND Ground. All GND pins must be connected.
3 to 10, 16 to
23, 41 to 48
G0 to G7,
B0 to B7,
R0 to R7
Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge of CLOCK.
R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the
regular printed circuit board (PCB) power or ground plane.
11
BLANK Composite Blank Control Input (TTL Compatible). A Logic 0 on this control input drives the analog outputs,
IOR, IOB, and IOG, to the blanking level. The
BLANK signal is latched on the rising edge of CLOCK. While
BLANK is a Logic 0, the R0 to R7, G0 to G7, and B0 to B7 pixel inputs are ignored.
12
SYNC Composite Sync Control Input (TTL Compatible). A Logic 0 on the SYNC input switches off a 40 IRE current
source. This is internally connected to the IOG analog output.
SYNC does not override any other control or
data input; therefore, it should only be asserted during the blanking interval. SYNC is latched on the rising
edge of CLOCK. If sync information is not required on the green channel, the
SYNC input should be tied to Logic 0.
13, 29, 30 V
AA
Analog Power Supply (5 V ± 5%). All V
AA
pins on the ADV7125 must be connected.
24 CLOCK
Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0 to R7, G0 to G7, B0 to B7,
SYNC, and
BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be
driven by a dedicated TTL buffer.
27, 31, 33
IOB, IOG,
IOR
Differential Blue, Green, and Red Current Outputs (High Impedance Current Sources). These RGB video
outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 Ω load. If
the complementary outputs are not required, these outputs should be tied to ground.
28, 32, 34
IOB, IOG,
IOR
Blue, Green, and Red Current Outputs. These high impedance current sources are capable of directly driving
a doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether
or not they are all being used.
35 COMP
Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 μF ceramic capacitor
must be connected between COMP and V
AA
.
36 V
REF
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

ADV7125KSTZ140

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Buy ADV7125KSTZ140
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 330MHz Triple 8B High Speed DAC
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