MT40A2G4TRF-093E:A Datasheet MT40A2G4TRF-093E:A, MT40A2G4TRF-083E:A | P10-P12

Table 5: Thermal Characteristics

Notes 1–3 apply to entire table

Parameter Symbol Value Units Notes

Operating temperature T

C

0 to 85 °C

0 to 95 °C 4

Notes:

1. MAX operating case temperature T

C

is measured in the center of the package, as shown

below.

2. A thermal solution must be designed to ensure that the device does not exceed the

maximum T

C

during operation.

3. Device functionality is not guaranteed if the device exceeds maximum T

C

during

operation.

4. If T

C

exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9µs

interval refresh rate. The use of self refresh temperature (SRT) or automatic self refresh

(ASR), if available, must be enabled.

Figure 4: Temperature Test Point Location

Test point

Length (L)

Width (W)

0.5 (W)

0.5 (L)

Table 6: Thermal Impedance

Package Substrate

Θ JA (°C/W)

Airflow =

0m/s

Θ JA (°C/W)

Airflow =

1m/s

Θ JA (°C/W)

Airflow =

2m/s Θ JB (°C/W) Θ JC (°C/W) Notes

78-ball Low

conductivity

51.0 39.2 34.7 12.7 2.2 1

High

conductivity

30.4 25.0 23.2

Note:

1. Thermal resistance data is based on a number of samples from multiple lots and should

be viewed as a typical number.

8Gb: x4, x8 TwinDie DDR4 SDRAM

Electrical Specifications – Leakages

PDF: 09005aef8549206e

DDR4_8Gb_x4_x8_2CS_TwinDie.pdf - Rev. B 09/15 EN

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Electrical Specifications – I

CDD

Parameters

Table 7: DDR4 I

CDD

Specifications and Conditions (Rev. A)

Note 1 applies to the entire table

Combined

Symbol

Individual

Die Status

Bus

Width DDR4-2133 DDR4-2400 Units

I

CDD0

I

CDD0

=

I

DD0

+ I

DD2P

+ 3

x4, x8 93 99 mA

I

CPP0

I

CPP0

=

I

PP0

+ I

PP3N

x4, x8 7 7 mA

I

CDD1

I

CDD1

=

I

DD1

+ I

DD2P

+ 3

x4, x8 98 103 mA

I

CDD2N

I

CDD2N

=

I

DD2N

+ I

DD2P

x4, x8 76 82 mA

I

CDD2NT

I

CDD2NT

=

I

DD2NT

+ I

DD2P

x4, x8 84 90 mA

I

CDD2P

I

CDD2P

=

I

DD2P

+ I

DD2P

x4, x8 60 64 mA

I

CDD2Q

I

CDD2Q

=

I

DD2Q

+ I

DD2P

x4, x8 69 73 mA

I

CDD3N

I

CDD3N

=

I

DD3N

+ I

DD2P

x4, x8 93 99 mA

I

CPP3N

I

CPP3N

=

I

PP3N

+ I

PP3N

x4, x8 6 6 mA

I

CDD3P

I

CDD3P

= I

DD3P

+ I

DD2P

x4, x8 74 76 mA

I

CDD4R

I

CDD4R

=

I

DD4R

+ I

DD2P

+ 3

x4, x8 183 195 mA

I

CDD4W

I

CDD4W

=

I

DD4W

+ I

DD2P

+ 3

x4, x8 193 215 mA

I

CDD5B

I

CDD5B

=

I

DD5B

+ I

DD2P

x4, x8 220 224 mA

I

CPP5B

I

CPP5B

=

I

PP5B

+ I

PP3N

x4, x8 25 25 mA

I

CDD6N

I

CDD6N

=

I

DD6N

+ I

DD6N

x4, x8 40 40 mA

I

CDD6E

I

CDD6E

=

I

DD6E

+ I

DD6E

x4, x8 54 54 mA

I

CDD6R

2

I

CDD6R

=

I

DD6R

+ I

DD6R

x4, x8 20 20 mA

I

CDD6A

(25°C)

2

I

CDD6A

=

I

DD6A

+ I

DD6A

x4, x8 18 18 mA

I

CDD6A

(45°C)

2

I

CDD6A

=

I

DD6A

+ I

DD6A

x4, x8 20 20 mA

I

CDD6A

(75°C)

2

I

CDD6A

=

I

DD6A

+ I

DD6A

x4, x8 32 32 mA

8Gb: x4, x8 TwinDie DDR4 SDRAM

Electrical Specifications – I

CDD

Parameters

PDF: 09005aef8549206e

DDR4_8Gb_x4_x8_2CS_TwinDie.pdf - Rev. B 09/15 EN

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Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 7: DDR4 I

CDD

Specifications and Conditions (Rev. A) (Continued)

Note 1 applies to the entire table

Combined

Symbol

Individual

Die Status

Bus

Width DDR4-2133 DDR4-2400 Units

I

CDD7

I

CDD7

=

I

DD7

+ I

DD2P

+ 3

x4, x8 218 245 mA

I

CPP7

I

CPP7

=

I

PP7

+ I

PP3N

x4, x8 15 17 mA

I

CDD8

I

CDD8

= I

DD8

+ I

DD8

x4, x8 36 36 mA

Notes:

1. I

CDD

values reflect the combined current of both individual die. I

DDx

represents individu-

al die values.

2. I

CDD6R

and I

CDD6A

values are typical.

8Gb: x4, x8 TwinDie DDR4 SDRAM

Electrical Specifications – I

CDD

Parameters

PDF: 09005aef8549206e

DDR4_8Gb_x4_x8_2CS_TwinDie.pdf - Rev. B 09/15 EN

12

Micron Technology, Inc. reserves the right to change products or specifications without notice.

MT40A2G4TRF-093E:A

MT40A2G4TRF-093E:A

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