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CY62177EV30LL-55BAXIT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
CY62177EV30 MoBL
®
Document Number: 001-09880 Rev. *N Page 10 of 18
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW)
[30]
Figure 10. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
[30, 32]
Switching Waveforms (continued)
VALID DATA
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
t
BW
NOTE 31
ADDRESS
CE
1
CE
2
BHE/BLE
WE
DATA I/O
t
HD
t
SD
t
SA
t
HA
t
AW
t
WC
VALID DATA
t
BW
t
SCE
t
PWE
NOTE 31
ADDRESS
CE
1
CE
2
BHE/BLE
WE
DATA I/O
Notes
30. If CE
1
goes HIGH and CE
2
goes LOW simultaneously with WE = V
IH
, the output remains in a high impedance state.
31. During this period the I/Os are in output state and input signals should not be applied.
32. The minimum write pulse width for Write Cycle No. 3 (WE
controlled, OE LOW) should be sum of t
SD
and t
HZWE
.
CY62177EV30 MoBL
®
Document Number: 001-09880 Rev. *N Page 11 of 18
Truth Table
CE
1
CE
2
WE OE BHE BLE Input/Output Mode Power
HX
[33]
XXX
[33]
X
[33]
High Z Deselect/Power Down Standby (I
SB
)
X
[33]
LXXX
[33]
X
[33]
High Z Deselect/Power Down Standby (I
SB
)
X
[33]
X
[33]
X X H H High Z Deselect/Power Down Standby (I
SB
)
L H H L L L Data Out (I/O
0
–I/O
15
) Read Active (I
CC
)
L H H L H L High Z (I/O
8
–I/O
15
);
Data Out (I/O
0
–I/O
7
)
Read Active (I
CC
)
LHHLLHData Out (I/O
8
–I/O
15
);
High Z (I/O
0
–I/O
7
)
Read Active (I
CC
)
L H L X L L Data In (I/O
0
–I/O
15
) Write Active (I
CC
)
L H L X H L High Z (I/O
8
–I/O
15
);
Data In (I/O
0
–I/O
7
)
Write Active (I
CC
)
L H L X L H Data In (I/O
8
–I/O
15
);
High Z (I/O
0
–I/O
7
)
Write Active (I
CC
)
L H H H L H High Z Output Disabled Active (I
CC
)
L H H H H L High Z Output Disabled Active (I
CC
)
L H H H L L High Z Output Disabled Active (I
CC
)
Note
33. The ‘X’ (Don’t care) state for the chip enables and byte enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these
pins is not permitted.
CY62177EV30 MoBL
®
Document Number: 001-09880 Rev. *N Page 12 of 18
Ordering Code Definitions
Ordering Information
Speed
(ns) Ordering Code
Package
Diagram
Package Type
Operating
Range
55 CY62177EV30LL-55ZXI 51-85183 48-pin TSOP I (12 × 18.4 × 1 mm) Pb-free Industrial
55 CY62177EV30LL-55BAXI 51-85191 48 ball FBGA (8 × 9.5 × 1.2 mm) Pb-free Industrial
Contact your local Cypress sales representative for availability of these parts.
Z = 48-pin TSOP I, BA = 48 ball FBGA
Temperature Grade:
I = Industrial
X = Pb-free
Package Type:
Speed Grade: 55 ns
Low Power
Voltage Range: V30 = 3 V (typical)
Process Technology: E = 90 nm
Bus Width = × 16
Density = 32-Mbit
621 = MoBL SRAM family
Company ID: CY = Cypress
621CY 7 V30
-
55 Z,BA IXLLE7
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

CY62177EV30LL-55BAXIT

Mfr. #:
Buy CY62177EV30LL-55BAXIT
Manufacturer:
Cypress Semiconductor
Description:
SRAM 32Mb 3V 55ns 2M x 16 LP SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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