AD7711AQ Datasheet AD7711ARZ, AD7711ANZ, AD7711ARZ-REEL | P19-P21

REV. G

–18–

AD7711

System calibration can also be used to remove any errors from

an antialiasing filter on the analog input. A simple R, C anti-

aliasing filter on the front end may introduce a gain error on the

analog input voltage, but the system calibration can be used to

remove this error.

System Offset Calibration

System offset calibration is a variation of both the system cali-

bration and self-calibration. In this case, the zero-scale point

for the system is presented to the AIN input of the converter.

System offset calibration is initiated by writing 1, 0, 0 to MD2,

MD1, MD0. The system zero-scale coefficient is determined by

converting the voltage applied to the AIN input, while the full-

scale coefficient is determined from the span between this AIN

conversion and a conversion on V

REF

. The zero-scale point

should be applied to the AIN input for the duration of the cali-

bration sequence. This is a one-step calibration sequence with

DRDY going low when the sequence is completed. In unipolar

mode, the system offset calibration is performed between the

two endpoints of the transfer function; in bipolar mode, it is

performed between midscale and positive full scale.

Background Calibration

The AD7711 also offers a background calibration mode where

the part interleaves its calibration procedure with its normal

conversion sequence. In the background calibration mode, the

same voltages are used as the calibration points that are used in

the self-calibration mode, that is, shorted inputs and V

REF

. The

background calibration mode is invoked by writing 1, 0, 1 to

MD2, MD1, MD0 of the control register. When invoked, the

background calibration mode reduces the output data rate of the

AD7711 by a factor of 6 while the –3 dB bandwidth remains

unchanged. The advantage is that the part is continually per-

forming calibration and automatically updating its calibration

coefficients. As a result, the effects of temperature drift, sup-

ply sensitivity, and time drift on zero- and full-scale errors are

automatically removed. When the background calibration mode

is turned on, the part will remain in this mode until Bits MD2,

MD1, and MD0 of the control register are changed. With back-

ground calibration mode on, the first result from the AD7711

will be incorrect because the full-scale calibration will not have

been performed. For a step change on the input, the second

output update will have settled to 100% of the final value.

Table VI summarizes the calibration modes and the calibration

points associated with them. It also gives the duration from

when the calibration is invoked to when valid data is available

to the user.

Table VI. Calibration Truth Table

Cal Type MD2, MD1, MD0 Zero-Scale Cal Full-Scale Cal Sequence Duration

Self-Cal 0, 0, 1 Shorted Inputs V

REF

One-Step 9 ¥ 1/Output Rate

System Cal 0, 1, 0 AIN Two-Step 4 ¥ 1/Output Rate

System Cal 0, 1, 1 AIN Two-Step 4 ¥ 1/Output Rate

System Offset Cal 1, 0, 0 AIN V

REF

One-Step 9 ¥ 1/Output Rate

Background Cal 1, 0, 1 Shorted Inputs V

REF

One-Step 6 ¥ 1/Output Rate

Span and Offset Limits

Whenever a system calibration mode is used, there are limits on

the amount of offset and span that can be accommodated. The

range of input span in both the unipolar and bipolar modes has a

minimum value of 0.8 ¥ V

REF

/GAIN and a maximum value of

2.1 ¥ V

REF

/GAIN.

The amount of offset that can be accommodated depends on

whether the unipolar or bipolar mode is being used. This offset

range is limited by the requirement that the positive full-scale

calibration limit is £ 1.05 ¥ V

REF

/GAIN. Therefore, the offset

range plus the span range cannot exceed 1.05 ¥ V

REF

/GAIN. If

the span is at its minimum (0.8 ¥ V

REF

/GAIN), the maximum

the offset can be is (0.25 ¥ V

REF

/GAIN).

In bipolar mode, the system offset calibration range is again

restricted by the span range. The span range of the converter in

bipolar mode is equidistant around the voltage used for the zero-

scale point; thus the offset range plus half the span range cannot

exceed (1.05 ¥ V

REF

/GAIN). If the span is set to 2 ¥ V

REF

/GAIN,

the offset span cannot move more than ± (0.05 ¥ V

REF

/GAIN)

before the endpoints of the transfer function exceed the input

overrange limits ± (1.05 ¥ V

REF

/GAIN). If the span range is set to

the minimum ± (0.4 ¥ V

REF

/GAIN), the maximum

allowable

offset range is ± (0.65

¥ V

REF

/GAIN).

POWER-UP AND CALIBRATION

On power-up, the AD7711 performs an internal reset that sets

the contents of the control register to a known state. However, to

ensure correct calibration for the device, a calibration routine

should be performed after power-up.

The power dissipation and temperature drift of the AD7711

are low, and no warm-up time is required before the initial

calibration is performed. However, if an external reference is

being used, this reference must have stabilized before calibra-

tion is initiated.

Drift Considerations

The AD7711 uses chopper stabilization techniques to minimize

input offset drift. Charge injection in the analog switches and dc

leakage currents at the sampling node are the primary sources of

offset voltage drift in the converter. The dc input leakage current is

essentially independent of the selected gain. Gain drift within the

converter depends primarily upon the temperature tracking of the

internal capacitors. It is not affected by leakage currents.

REV.G

AD7711

–19–

Measurement errors due to offset drift or gain drift can be elimi-

nated at any time by recalibrating the converter or by operating

the part in the background calibration mode. Using the system

calibration mode can also minimize offset and gain errors in the

signal conditioning circuitry. Integral and differential linearity

errors are not significantly affected by temperature changes.

POWER SUPPLIES AND GROUNDING

Because the analog inputs and reference input are differential,

most of the voltages in the analog modulator are common-mode

voltages. V

BIAS

provides the return path for most of the analog

currents flowing in the analog modulator. As a result, the V

BIAS

input should be driven from a low impedance to minimize errors

due to charging/discharging impedances on this line. When the

internal reference is used as the reference source for the part,

AGND is the ground return for this reference voltage.

The analog and digital supplies to the AD7711 are independent

and separately pinned out to minimize coupling between the

analog and digital sections of the device. The digital filter will

provide rejection of broadband noise on the power supplies,

except at integer multiples of the modulator sampling frequency.

The digital supply (DV

) must not exceed the analog positive

supply (AV

) by more than 0.3 V in normal operation. If separate

analog and digital supplies are used, the recommended decoupling

scheme is shown in Figure 9. In systems where AV

= 5 V and

= 5 V, it is recommended that AV

and DV

are

driven from the same 5 V supply, although each supply should be

decoupled separately as shown in Figure 9. It is preferable that

the common supply is the system’s analog 5 V supply.

It is also important that power is applied to the AD7711 before

signals at REF IN, AIN, or the logic input pins in order to avoid

latch-up. If separate supplies are used for the AD7711 and the

system digital circuitry, the AD7711 should be powered up first.

If it is not possible to guarantee this, current limiting resistors

should be placed in series with the logic inputs.

AD7711

0.1␮F10␮F

ANALOG

SUPPLY

0.1␮F

DIGITAL 5V

SUPPLY

Figure 9. Recommended Decoupling Scheme

DIGITAL INTERFACE

The AD7711’s serial communications port provides a flexible

arrangement to allow easy interfacing to industry-standard

microprocessors, microcontrollers, and digital signal processors.

A serial read to the AD7711 can access data from the output

write to the AD7711 can write data to the control register or the

calibration registers.

Two different modes of operation are available, optimized for

different types of interfaces where the AD7711 can act either as

master in the system (it provides the serial clock) or as slave (an

external serial clock can be provided to the AD7711). These

two modes, labelled self-clocking mode and external clocking

mode, are discussed in detail in the following sections.

REV. G

–20–

AD7711

Self-Clocking Mode

The AD7711 is configured for its self-clocking mode by tying

the MODE pin high. In this mode, the AD7711 provides the

serial clock signal used for the transfer of data to and from the

AD7711. This self-clocking mode can be used with processors

that allow an external device to clock their serial port, including

most digital signal processors and microcontrollers such as the

68HC11 and 68HC05. It also allows easy interfacing to serial-

parallel conversion circuits in systems with parallel data commu-

nication, allowing interfacing to 74XX299 universal shift

registers without any additional decoding. In the case of shift

registers, the serial clock line should have a pull-down resistor

instead of the pull-up resistor shown in Figures 10 and 11.

Read Operation

Data can be read from either the output register, the control

data read accesses data from the control register or from the

output/calibration registers. This A0 signal must remain valid

for the duration of the serial read operation. With A0 high, data

is accessed from either the output register or the calibration

registers. With A0 low, data is accessed from the control register.

The function of the DRDY line is dependent only on the output

update rate of the device and the reading of the output data

the output data register. It is reset high when the last bit of data

(either 16th bit or 24th bit) is read from the output register. If

data is not read from the output register, the DRDY line re-

mains low. The output register continues to be updated at the

output update rate but DRDY will not indicate this. A read

from the device in this circumstance accesses the most recent

word in the output register. If a new data-word becomes available

to the output register while data is being read from the output

will be lost to the user. DRDY is not affected by reading from

the control register or the calibration registers.

MSB LSB

THREE-STATE

SDATA (O)

SCLK (O)

RFS (I)

A0 (I)

DRDY (O)

Figure 10. Self-Clocking Mode, Output Data Read Operation

Data can be accessed from the output data register only when

DRDY is low. If RFS goes low with DRDY high, no data trans-

fer takes place. DRDY does not have any effect on reading data

from the control register or from the calibration registers.

Figure 10 shows a timing diagram for reading from the AD7711

in the self-clocking mode. The read operation shows a read from

the AD7711’s output data register. A read from the control

DRDY line is not related to the read function. Depending on

the output update rate, it can go low at any stage in the control/

calibration register read cycle without affecting the read, and its

status should be ignored. A read operation from either the con-

trol or calibration registers must always read 24 bits of data

from the respective register.

Figure 10 shows a read operation from the AD7711. For the

timing diagram shown, it is assumed that there is a pull-up

resistor on the SCLK output. With DRDY low, the RFS

input is brought low. RFS going low enables the serial clock of

the AD7711 and also places the MSB of the word on the serial

data line. All subsequent data bits are clocked out on a high to

low transition of the serial clock and are valid prior to the follow-

ing rising edge of this clock. The final active falling edge of

SCLK clocks out the LSB, and this LSB is valid prior to the final

active rising edge of SCLK. Coincident with the next falling

edge of SCLK, DRDY is reset high. DRDY going high turns off

the SCLK and the SDATA outputs, which means the data hold

time for the LSB is slightly shorter than for all other bits.

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AD7711AQ

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