1
Features
Low-voltage and Standard-voltage Operation
5.0 (V
CC
= 4.5V to 5.5V)
2.7 (V
CC
= 2.7V to 5.5V)
2.5 (V
CC
= 2.5V to 5.5V)
1.8 (V
CC
= 1.8V to 3.6V)
Internally Organized 16,384 x 8 and 32,768 x 8
2-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
1 MHz (5V), 400 kHz (2.7V, 2.5V) and 100 kHz (1.8V) Compatibility
Write Protect Pin for Hardware and Software Data Protection
64-byte Page Write Mode (Partial Page Writes Allowed)
Self-timed Write Cycle (5 ms Typical)
High Reliability
Endurance: 100,000 Write Cycles
Data Retention: 40 Years
ESD Protection: >4000V
Automotive Grade and Extended Temperature Devices Available
8-pin JEDEC PDIP, 8-pin JEDEC and EIAJ SOIC, 14-pin TSSOP, 8-pin Leadless Array,
and 8-ball dBGA
TM
Packages
Description
The AT24C128/256 provides 131,072/262,144 bits of serial electrically erasable and
programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8
bits each. The device’s cascadable feature allows up to 4 devices to share a common
2-wire bus. The device is optimized for use in many industrial and commercial applica-
tions where low power and low voltage operation are essential. The devices are
available in space-saving 8-pin JEDEC PDIP, 8-pin EIAJ, 8-pin JEDEC SOIC, 14-pin
TSSOP, 8-pin LAP, and 8-ball dBGA packages. In addition, the entire family is avail-
able in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V (2.5V to 5.5V) and 1.8V (1.8V to
3.6V) versions.
2-wire Serial
EEPROMs
128K (16,384 x 8)
256K (32,768 x 8)
AT24C128
AT24C256
Rev. 0670E–07/01
Pin Configurations
Pin Name Function
A0 - A1 Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
NC No Connect
8-pin PDIP
1
2
3
4
8
7
6
5
A0
A1
NC
GND
VCC
WP
SCL
SDA
8-pin SOIC
1
2
3
4
8
7
6
5
A0
A1
NC
GND
VCC
WP
SCL
SDA
8-pin Leadless Array
Bottom View
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
NC
GND
14-pin TSSOP
1
2
3
4
5
6
7
14
13
12
11
10
9
8
A0
A1
NC
NC
NC
NC
GND
VCC
WP
NC
NC
NC
SCL
SDA
8-ball dBGA
Bottom View
VCC
WP
SCL
SDA
A0
A1
NC
GND
1
2
3
4
8
7
6
5
2
AT24C128/256
0670E07/01
Block Diagram
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
*NOTICE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
3
AT24C128/256
0670E07/01
Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-
drain driven and may be wire-ORed with any number of other open-drain or open collector
devices.
DEVICE/PAGE ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that
are hardwired or left not connected for hardware compatibility with AT24C32/64. When the
pins are hardwired, as many as four 128K/256K devices may be addressed on a single bus
system (device addressing is discussed in detail under the Device Addressing section). When
the pins are not hardwired, the default A
1
and A
0
are zero.
WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write oper-
ations. When WP is tied high to V
CC
, all write operations to the memory are inhibited. If left
unconnected, WP is internally pulled down to GND. Switching WP to V
CC
prior to a write oper-
ation creates a software write protect function.
Memory
Organization
AT24C128/256, 128K/256K SERIAL EEPROM: The 128K/256K is internally organized as
256/512 pages of 64-bytes each. Random word addressing requires a 14/15-bit data word
address.

AT24C256W-10SI

Mfr. #:
Manufacturer:
Description:
IC EEPROM 256K I2C 1MHZ 8SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union