Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
7
Rev. D
12/13/2007
IS62WV51216ALL, IS62WV51216BLL
IS62WV51216BLL, POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter Test Conditions Max. Max. Max. Unit
45 55 70
I
CC VDD Dynamic Operating VDD = Max., Com. 35 30 25 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. 40 35 30
I
CC1 Operating Supply VDD = Max., CS1 = 0.2V Com. 5 5 5 mA
Current WE = VDD – 0.2V Ind. 5 5 5
CS2 = VDD – 0.2V, f = 1MHZ
ISB1 TTL Standby Current VDD = Max., Com. 0.3 0.3 0.3 mA
(TTL Inputs) VIN = VIH or VIL Ind. 0.3 0.3 0.3
CS1 = VIH , CS2 = VIL,
f = 1 MHZ
OR
ULB Control
VDD = Max., VIN = VIH or VIL
CS1 = VIL, f = 0, UB = VIH, LB = VIH
ISB2 CMOS Standby VDD = Max., Com. 20 20 20 µA
Current (CMOS Inputs) CS1
V DD – 0.2V, Ind. 25 25 25
CS2
0.2V, typ.
(2)
444
VIN
V DD – 0.2V, or
VIN
0.2V, f = 0
OR
ULB Control VDD = Max., CS1 = VIL, CS2=VIH
VIN
V DD – 0.2V, or VIN
0.2V, f = 0;
UB / LB = VDD – 0.2V
Note:
1. At f = f
MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 3.0V, TA = 25
o
C and not 100% tested.
8
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. D
12/13/2007
IS62WV51216ALL, IS62WV51216BLL
DATA VALID
PREVIOUS DATA VALID
tAA
tOHA
tOHA
tRC
DQ0-D15
ADDRESS
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
(Address Controlled) (CS1 = OE = VIL, CS2 = WE = VIH, UB or LB = VIL)
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
45 ns 55 ns 70 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 45 55 70 ns
tAA Address Access Time 45 55 70 ns
tOHA Output Hold Time 10 10 10 ns
tACS1/tACS2 CS1/CS2 Access Time 45 55 70 ns
tDOE OE Access Time 20 25 35 ns
tHZOE
(2)
OE to High-Z Output 15 20 25 ns
tLZOE
(2)
OE to Low-Z Output 5 5 5 ns
tHZCS1/tHZCS2
(2)
CS1/CS2 to High-Z Output 0 15 0 20 0 25 ns
tLZCS1/tLZCS2
(2)
CS1/CS2 to Low-Z Output 10 10 10 ns
tBA LB, UB Access Time 45 55 70 ns
tHZB LB, UB to High-Z Output 0 15 0 20 0 25 ns
tLZB LB, UB to Low-Z Output 0 0 0 ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to
V
DD-0.2V/0.4V to VDD-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
9
Rev. D
12/13/2007
IS62WV51216ALL, IS62WV51216BLL
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE1/
t
ACE2
t
LZCE1/
t
LZCE2
t
HZOE
HIGH-Z
DATA VALID
t
HZCS1/
t
HZCS1
ADDRESS
OE
CS1
s
CS2s
DOUT
LBs
,
UBs
t
HZB
t
BA
t
LZB
AC WAVEFORMS
READ CYCLE NO. 2
(1,3)
(CS1, CS2, OE, AND UB/LB Controlled)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS1, UB, or LB = V
IL. CS2=WE=VIH.
3. Address is valid prior to or coincident with CS1 LOW transition.

IS62WV51216ALL-70BI

Mfr. #:
Manufacturer:
ISSI
Description:
SRAM 8Mb 512Kx16 70ns Async SRAM
Lifecycle:
New from this manufacturer.
Delivery:
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