LTC3858-2
25
38582f
APPLICATIONS INFORMATION
Note that the LTC3858-2 can only be synchronized to an
external clock whose frequency is within range of the
LTC3858-2’s internal VCO, which is nominally 55kHz to
1MHz. This is guaranteed to be between 75kHz and 850kHz.
Typically, the external clock (on the PLLIN/MODE pin) input
high threshold is 1.6V, while the input low threshold is 1.1V.
Rapid phase-locking can be achieved by using the FREQ
pin to set a free-running frequency near the desired
synchronization frequency. The VCO’s input voltage is
prebiased at a frequency corresponding to the frequency
set by the FREQ pin. Once prebiased, the PLL only needs
to adjust the frequency slightly to achieve phase-locking
and synchronization. Although it is not required that the
free-running frequency be near external clock frequency,
doing so will prevent the operating frequency from passing
through a large range of frequencies as the PLL locks.
Table 3 summarizes the different states in which the FREQ
pin can be used.
Table 3
FREQ PIN PLLIN/MODE PIN FREQUENCY
0V DC Voltage 350kHz
INTV
CC
DC Voltage 535kHz
Resistor DC Voltage 50kHz to 900kHz
Any of the Above External Clock Phase-Locked to
External Clock
Minimum On-Time Considerations
Minimum on-time, t
ON(MIN)
, is the smallest time dura-
tion that the LTC3858-2 is capable of turning on the top
MOSFET. It is determined by internal timing delays and the
gate charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
t
ON(MIN)
<
V
OUT
V
IN
f
()
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3858-2 is approximately
95ns. However, as the peak sense voltage decreases the
minimum on-time gradually increases up to about 130ns.
This is of particular concern in forced continuous applica-
tions with low ripple current at light loads. If the duty cycle
drops below the minimum on-time limit in this situation,
a significant amount of cycle skipping can occur with cor-
respondingly larger current and voltage ripple.
Figure 10. Relationship Between Oscillator Frequency
and Resistor Value at the FREQ Pin
FREQ PIN RESISTOR (k)
15
FREQUENCY (kHz)
600
800
1000
35 45 5525
38582 F10
400
200
500
700
900
300
100
0
65 75 85 95 105 115
125
LTC3858-2
26
38582f
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC3858-2 circuits: 1) IC V
IN
current, 2) IN-
TV
CC
regulator current, 3) I
2
R losses, 4) topside MOSFET
transition losses.
1. The V
IN
current is the DC input supply current given
in the Electrical Characteristics table, which excludes
MOSFET driver and control currents. V
IN
current typi-
cally results in a small (<0.1%) loss.
2. INTV
CC
current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched
from low to high to low again, a packet of charge, dQ,
moves from INTV
CC
to ground. The resulting dQ/dt is
a current out of INTV
CC
that is typically much larger
than the control circuit current. In continuous mode,
I
GATECHG
= f(Q
T
+ Q
B
), where Q
T
and Q
B
are the gate
charges of the topside and bottom side MOSFETs.
Supplying INTV
CC
from an output-derived power source
through EXTV
CC
will scale the V
IN
current required for
the driver and control circuits by a factor of (Duty Cycle)/
(Efficiency). For example, in a 20V to 5V application,
10mA of INTV
CC
current results in approximately 2.5mA
of V
IN
current. This reduces the midcurrent loss from
10% or more (if the driver was powered directly from
V
IN
) to only a few percent.
APPLICATIONS INFORMATION
3. I
2
R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resis-
tor, and input and output capacitor ESR. In continuous
mode the average output current flows through L and
R
SENSE
, but is “chopped” between the topside MOSFET
and the synchronous MOSFET. If the two MOSFETs have
approximately the same R
DS(ON)
, then the resistance
of one MOSFET can simply be summed with the resis-
tances of L, R
SENSE
and ESR to obtain I
2
R losses. For
example, if each R
DS(ON)
= 30m, R
L
= 50m, R
SENSE
= 10m and R
ESR
= 40m (sum of both input and
output capacitance losses), then the total resistance
is 130m. This results in losses ranging from 3% to
13% as the output current increases from 1A to 5A for
a 5V output, or a 4% to 20% loss for a 3.3V output.
Efficiency varies as the inverse square of V
OUT
for the
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (t
y
pically 15V or greater). Transition
losses can be estimated from:
Transition Loss = (1.7) • V
IN
• 2 • I
O(MAX)
• C
RSS
• f
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is
very important to include these “system” level losses
during the design phase. The internal battery and fuse
resistance losses can be minimized by making sure that
C
IN
has adequate charge storage and very low ESR at
the switching frequency. A 25W supply will typically
require a minimum of 20µF to 40µF of capacitance
having a maximum of 20m to 50m of ESR. The
LTC3858-2 2-phase architecture typically halves this
input capacitance requirement over competing solu-
tions. Other losses including Schottky conduction losses
during dead-time and inductor core losses generally
account for less than 2% total additional loss.
LTC3858-2
27
38582f
APPLICATIONS INFORMATION
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
OUT
shifts by an
amount equal to ΔI
LOAD
(ESR), where ESR is the effective
series resistance of C
OUT
. ΔI
LOAD
also begins to charge or
discharge C
OUT
generating the feedback error signal that
forces the regulator to adapt to the current change and
return V
OUT
to its steady-state value. During this recovery
time V
OUT
can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. OPTI-
LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values. The availability of the I
TH
pin not only allows
optimization of control loop behavior, but it also provides
a DC coupled and AC filtered closed-loop response test
point. The DC step, rise time and settling at this test
point truly reflects the closed-loop response. Assuming
a predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also
be estimated by examining the rise time at the pin. The
I
TH
external components shown in Figure 13 circuit will
provide an adequate starting point for most applications.
The I
TH
series R
C
-C
C
filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1µs to 10µs will
produce output voltage and I
TH
pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop.
Placing a resistive load and a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
is why it is better to look at the I
TH
pin signal which is in
the feedback loop and is the filtered and compensated
control loop response.
The gain of the loop will be increased by increasing R
C
and the bandwidth of the loop will be increased by de-
creasing C
C
. If R
C
is increased by the same factor that C
C
is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual overall
supply performance.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
LOAD
to C
OUT
is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • C
LOAD
. Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.

LTC3858IUH-2#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Low IQ, Dual, 2-Phase Synchronous Step-Down Controller without OVP
Lifecycle:
New from this manufacturer.
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