IRF8301MTRPbF
www.irf.com © 2013 International Rectifier September 6, 2013
8
Fig 19. Diode Reverse Recovery Test Circuit for HEXFET
®
Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple ≤ 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P. W .
Period
*** V
GS
= 5V for Logic Level Devices
***
+
-
+
+
+
-
-
-
R
G
V
DD
• dv/dt controlled by R
G
• Driver same type as D.U.T.
• I
SD
controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
**
*
* Use P-Channel Driver for P-Channel Measurements
** Reverse Polarity for P-Channel
DirectFET Board Footprint, MT Outline
(Medium Size Can, T-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.
G = GATE
D = DRAIN
S = SOURCE
G
D
DD
D
S
S
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
