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STA120
Control Pins
1 C Channel Status Output. Received channel status bit serial output port. FSYNC may be used to
latch this bit externally. Except in I
2
S modes when this pin is updated at the active edge off
Fsync.
2 Cd Channel Status Output Bits.These pin are dual Function with the "C" bits selected when SEL is
high. Channel status information is displayed for the channel selected by CS12. C0
, which is
channel status bit 0, defines professional (C0
= 0) or consumer (C0 = 1) mode and further
controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.
F1 Frequency reporting Bits.Encoder sample frequency information that is enabled by bringing SEL
low. A proper clock on FCK must be input for at least two thirds of a channel status block for
these pins to be valid. They are updated three times per block, starting at the block boundary.
3 Cc Channel Status Output Bits.These pin are dual Function with the "C" bits selected when SEL is
high. Channel status information is displayed for the channel selected by CS12. C0
, which is
channel status bit 0, defines professional (C0
= 0) or consumer (C0 = 1) mode and further
controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.
F0 Frequency reporting Bits.Encoded sample frequency information that is enabled by bringing SEL
low. A proper clock on FCK must be input for at least two thirds of a channel status block for
these pins to be valid. They are updated three times per block, starting at the block boundary.
4 Cb Channel Status Output Bits.These pin are dual Function with the "C" bits selected when SEL is
high. Channel status information is displayed for the channel selected by CS12. C0
, which is
channel status bit 0, defines professional (C0
= 0) or consumer (C0 = 1) mode and further
controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.
E2 Error Condition.Encoded error information that is enabled by bringing SEL low. The error codes
are prioritized and latched so that the error code displayed is the highest level of error since the
last clearing of the error pins. Clearing is accomplished by bringing SEL high for more than 8
MCK cycles.
5 Ca Channel Status Output Bits.These pin are dual Function with the "C" bits selected when SEL is
high. Channel status information is displayed for the channel selected by CS12. C0
, which is
channel status bit 0, defines professional (C0
= 0) or consumer (C0 = 1) mode and further
controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.
5 E2 Error Condition.Encoded error information that is enabled by bringing SEL low. The error codes
are prioritized and latched so that the error code displayed is the highest level of error since the
last clearing of the error pins. Clearing is accomplished by bringing SEL high for more than 8
MCK cycles.
6C0
Channel Status Output Bits.These pin are dual Function with the "C" bits selected when SEL is
high. Channel status information is displayed for the channel selected by CS12. C0
, which is
channel status bit 0, defines professional (C0
= 0) or consumer (C0 = 1) mode and further
controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.
E0 Error Condition.Encoded error information that is enabled by bringing SEL low. The error codes
are prioritized and latched so that the error code displayed is the highest level of error since the
last clearing of the error pins. Clearing is accomplished by bringing SEL high for more than 8
MCK cycles.
13 CS12 Channel Select.This pin is also dual function and is selected by bringing SEL high. CS12 selects
sub-frame1 (when low) or sub-frame2 (when high) to be displayed by channel status pins C0
an
Ca through Ce.
FCK Frequency Clock.Frequency Clock input that is enabled by bringing SEL low. FCK is compared to
the received clock frequency with the value displayed on F2 through F0. Nominal input value is
6.144MHz.
14 U User Bit.Received user bit serial output port, FSYNC may be used to latch this bit externally.
Except in I2S modes when this pin is updated at the active edge off Fsync.
15 CBL Channel Status Block Start.The channel status block output is high for the first four bytes of
channel status and low for the last 20 bytes.
PINS DESCRIPTION
(continued)
N. Name Description
