NB6N239S
http://onsemi.com
7
Application Information
The NB6N239S is a high−speed, low skew clock divider
with two divider circuits, each having selectable clock
divide ratios; B1/2/4/8 and B2/4/8/16. Both divider
circuits drive differential LVDS compatible outputs. The
internal dividers are synchronous to each other. Therefore,
the common output edges are precisely aligned.
The NB6N239S clock inputs can be driven by a variety of
differential signal level technologies including LVDS,
LVPECL, HCSL, HSTL, or CML. The differential clock
input buffer employs a pair of internal 50 W termination
resistors in a 100 W center−tapped configuration and
accessible via the VT pin. This feature provides
transmission line termination on−chip, at the receiver end,
eliminating external components. The V
BBAC
reference
output is recommended to be used to rebias differential or
single−ended input capacitor−coupled CLOCK signals. For
the capacitor−coupled CLK and/or CLK
inputs, V
BBAC
should be connected to the V
T
pin and bypassed to ground
with a 0.01 mF capacitor. Inputs CLK and CLK
must be
signal driven or auto oscillation may result.
The common enable (EN
) is synchronous so that the
internal divider flip−flops will only be enabled/disabled
when the internal clock is in the LOW state. This avoids any
chance of generating a runt pulse on the internal clock when
the device is enabled/disabled, as can happen with an
asynchronous control. The internal enable flip−flop is
clocked on the falling edge of the input clock. Therefore, all
associated specification limits are referenced to the negative
edge of the clock input.
CLK
Q (÷2)
Q (÷4)
Q (÷8)
Figure 4. Timing Diagram
Q (÷16)
Q (÷1)
MR
Figure 5. Master Reset Timing Diagram
CLK
MR
Q (÷n)
t
RR
NOTE: On the rising edge of MR, Q goes HIGH after the first rising edge of CLK.
t
RR
