18
INDUSTRIAL TEMPERATURE RANGE
IDT5T9820
EEPROM PROGRAMMABLE 2.5V ZERO DELAY PLL CLOCK DRIVER
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
All outputs at the same interface level
Symbol Parameter Min. Typ. Max Unit
FNOM VCO Frequency Range see JTAG/I
2
C Serial Configurations: VCO Frequency Range table
tRPW Reference Clock Pulse Width HIGH or LOW 1 — — ns
tFPW Feedback Input Pulse Width HIGH or LOW 1 — — ns
tSK(B) Output Matched Pair Skew
(1,2,4)
——50ps
tSK(O) Output Skew (Rise-Rise, Fall-Fall, Nominal)
(1,3)
— — 100 ps
tSK1(ω) Multiple Frequency Skew (Rise-Rise, Fall-Fall, Nominal-Divided, Divided-Divided)
(1,3,4)
— — 100 ps
tSK2(ω) Multiple Frequency Skew (Rise-Fall, Nominal-Divided, Divided-Divided)
(1,3,4)
— — 400 ps
tSK1(INV) Inverting Skew (Nominal-Inverted)
(1,3)
——400 ps
tSK2(INV) Inverting Skew (Rise-Rise, Fall-Fall, Rise-Fall, Inverted-Divided)
(1,3,4)
— — 400 ps
tSK(PR) Process Skew
(1,3.5)
——300 ps
t(φ) REF Input to FB Static Phase Offset
(6)
-100 — 100 ps
t
ODCV Output Duty Cycle Variation from 50%
(7)
HSTL / eHSTL / 1.8V LVTTL -375 — 375 ps
2.5V LVTTL -275 — 275
t
ORISE Output Rise Time
(8)
HSTL / eHSTL / 1.8V LVTTL — — 1.2 ns
2.5V LVTTL — — 1
t
OFALL Output Fall Time
(8)
HSTL / eHSTL / 1.8V LVTTL — — 1.2 ns
2.5V LVTTL — — 1
tL Power-up PLL Lock Time
(9)
—— 4ms
tL(ω) PLL Lock Time After Input Frequency Change
(9)
—— 1ms
tL(REFSEL1) PLL Lock Time After Change in REF_SEL
(9,11)
— — 100 µs
tL(REFSEL2) PLL Lock Time After Change in REF_SEL (REF1 and REF0 are different frequency)
(9)
—— 1ms
tL(PD) PLL Lock Time After Asserting PD Pin
(9)
—— 1ms
tJIT(CC) Cycle-to-Cycle Output Jitter (peak-to-peak)
(10)
— 50 75 ps
tJIT(PER) Period Jitter (peak-to-peak)
(10)
——75 ps
tJIT(HP) Half Period Jitter (peak-to-peak, QFB/QFB only)
(10, 12)
— — 125 ps
tJIT(DUTY) Duty Cycle Jitter (peak-to-peak)
(10)
——100 ps
V
OX HSTL and eHSTL Differential True and Complementary Output Crossing Voltage Level VDDQN/2 - 150 VDDQN/2 VDDQN/2 + 150 mV
QFB/QFB only
(12)
NOTES:
1. Skew is the time between the earliest and latest output transition among all outputs when all outputs are loaded with the specified load.
2. tSK(B) is the skew between a pair of outputs (nQ0 and nQ1) when all outputs are selected as the same class.
3. The measurement is made at VDDQN/2.
4. There are three classes of outputs: nominal (zero delay), inverted, and divided (divide-by-2 or divide-by-4 mode).
5. tSK(PR) is the output to corresponding output skew between any two devices operating under the same conditions (VDD and VDDQN, ambient temperature, air flow, etc.).
6. t(φ) is measured with REF and FB the same type of input, the same rise and fall times. For 1.8V / 2.5V LVTTL input and output, the measurement is taken from VTHI on REF
to VTHI on FB. For HSTL / eHSTL input and output, the measurement is taken from the crosspoint of REF/REF to the crosspoint of FB/FB. All outputs are set to zero delay,
FB input divider set to divide-by-one, and Bit 60 = 1.
7. tODCV is measured with all outputs selected for zero delay.
8. Output rise and fall times are measured between 20% to 80% of the actual output voltage swing.
9. tL, tL(ω), tL(REFSEL1), tL(REFSEL2), and tL(PD) are the times that are required before the synchronization is achieved. These specifications are valid only after VDD/VDDQN is stable and
within the normal operating limits. These parameters are measured from the application of a new signal at REF or FB, or after PD is (re)asserted until t(φ) is within specified
limits.
10. The jitter parameters are measured with all outputs selected for zero delay, FB input divider is set to divide-by-one, and Bit 60 = 1.
11. Both REF inputs must be the same frequency, but up to ±180° out of phase.
12. For HSTL/eHSTL outputs only.
