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LTC1702IGN#PBF

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LTC1702
1702fa
Maximizing Low Load Current Efficiency
Low load current efficiency depends strongly on proper
operation in discontinuous and Burst Mode operations. In
an ideally optimized system, discontinuous mode reduces
conduction losses but not switching losses, since each
power MOSFET still switches on and off once per cycle. In
a typical system, there is additional loss in discontinuous
mode due to a small amount of residual current left in the
inductor when QB turns off. This current gets dissipated
across the body diode of either QT or QB. Some LTC1702
systems lose as much to body diode conduction as they
save in MOSFET conduction. The real efficiency benefit of
discontinuous mode happens when Burst Mode operation
is invoked. At typical power levels, when Burst Mode
operation is activated, gate drive is the dominant loss
term. Burst Mode operation turns off all output switching
for several clock cycles in a row, significantly cutting gate
drive losses. As the load current in Burst Mode operation
falls toward zero, the current drawn by the circuit falls to
the LTC1702’s background quiescent level—about 3mA
per channel.
To maximize low load efficiency, make sure the LTC1702
is allowed to enter discontinuous and Burst Mode opera-
tion as cleanly as possible. FCB must be above its 0.8V
threshold. Minimize ringing at the SW node so that the
discontinuous comparator leaves as little residual current
in the inductor as possible when QB turns off. It helps to
connect the SW pin of the LTC1702 as close to the drain
of QB as possible. An RC snubber network can also be
added from SW to PGND.
REGULATION OVER COMPONENT TOLERANCE/
TEMPERATURE
DC Regulation Accuracy
The LTC1702 initial DC output accuracy depends mainly
on internal reference accuracy, op amp offset and external
resistor accuracy. Two LTC1702 specs come into play:
feedback voltage and feedback voltage line regulation. The
feedback voltage spec is 800mV ± 8mV over the full
temperature range, and is specified at the FB pin, which
encompasses both reference accuracy and any op amp
offset. This accounts for 1% error at the output with a 5V
input supply. The feedback voltage line regulation spec
adds an additional 0.05%/V term that accounts for change
in reference output with change in input supply voltage.
With a 5V supply, the errors contributed by the LTC1702
itself add up to no more than 1% DC error at the output.
The output voltage setting resistors (R1 and R
B
in
Figure 3) are the other major contributor to DC error. At a
typical 1.xV output voltage, the resistors are of roughly the
same value, which tends to halve their error terms, im-
proving accuracy. Still, using 1% resistors for R1 and R
B
will add 1% to the total output error budget, equal to that
of all errors due to the LTC1702 combined. Using 0.1%
resistors in just those two positions can nearly halve the
DC output error for very little additional cost.
Load Regulation
Load regulation is affected by feedback voltage, feedback
amplifier gain and external ground drops in the feedback
path. Feedback voltage is covered above and is within 1%
over temperature. A full-range load step might require a
10% duty cycle change to keep the output constant,
requiring the COMP pin to move about 100mV. With
amplifier gain at 85dB, this adds up to only a 10µV shift at
FB, negligible compared to the reference accuracy terms.
External ground drops aren’t so negligible. The LTC1702
can sense the positive end of the output voltage by
attaching the feedback resistor directly at the load, but it
cannot do the same with the ground lead. Just 0.001Ω of
resistance in the ground lead at 10A load will cause a 10mV
error in the output voltage—as much as all the other DC
errors put together. Proper layout becomes essential to
achieving optimum load regulation from the LTC1702.
See the Layout/Troubleshooting section for more infor-
mation. A properly laid out LTC1702 circuit should move
less than a millivolt at the output from zero to full load.
TRANSIENT RESPONSE
Transient response is the other half of the regulation
equation. The LTC1702 can keep the DC output voltage
constant to within 1% when averaged over hundreds of
APPLICATIONS INFORMATION
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29
LTC1702
1702fa
cycles. Over just a few cycles, however, the external
components conspire to limit the speed that the output
can move. Consider our typical 5V to 1.6V circuit, sub-
jected to a 1A to 5A load transient. Initially, the loop is in
regulation and the DC current in the output capacitor is
zero. Suddenly, an extra 4A start flowing out of the output
capacitor while the inductor is still supplying only 1A. This
sudden change will generate a (4A)(C
ESR
)voltage step at
the output; with a typical 0.015Ω output capacitor ESR,
this is a 60mV step at the output, or 3.8% (for a 1.6V output
voltage).
Very quickly, the feedback loop will realize that something
has changed and will move at the bandwidth allowed by
the external compensation network towards a new duty
cycle. If the bandwidth is set to 50kHz, the COMP pin will
get to 60% of the way to 90% duty cycle in 3µs. Now the
inductor is seeing 3.5V across itself for a large portion of
the cycle, and its current will increase from 1A at a rate set
by di/dt = V/L. If the inductor value is 0.5µH, the di/dt will
be 3.5V/0.5µH or 7A/µs. Sometime in the next few micro-
seconds after the switch cycle begins, the inductor current
will have risen to the 5A level of the load current and the
output capacitor will stop losing charge.
Note that the output voltage will stop dropping before the
inductor current reaches this new output current level.
Recall that any practical output capacitor looks like a pure
capacitance in series with some amount of ESR. When a
load transient hits, virtually all of the initial voltage drop at
the output is due to IR drop across the ESR. The output
capacitance begins to discharge at the same time and
continues until the inductor current rises to match the new
output current level.
The output voltage, however, will turn around and start
heading the right way before this happens. The next time
the top MOSFET turns on, the inductor current will begin
increasing linearly. This increasing current flows almost
entirely into the capacitor, going through the ESR as it
does so (Figure 16). Positive di/dt in the inductor causes
positive dv/dt in the ESR, regardless of what the “pure”
capacitance is doing. The output voltage will turn around
when the positive dv/dt across the ESR exceeds the
negative dv/dt across the pure capacitance. If the expected
load step (∆I) is known, an optimum inductor value can be
chosen:
LV V C
ESR
I
IN OUT
≤
()
∆
–••
APPLICATIONS INFORMATION
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+
–
–
I
L
V
OUT
I
OUT
1702 F16a
V
ESR
C
OUT
V
CAP
V
SW
L
+
V
CAP
V
OUT
TRANSIENT
HITS
V
OUT
TURNS
AROUND
I
L
> I
OUT
TIME
V
ESR
I
OUT
I
L
V
OUT
V
ESR
I
OUT
I
L
V
CAP
V
OUT(NOMINAL)
1702 F16b
Figure 16b. Transient Recovery Curves
Figure 16a. Capacitor Parasitics
Affecting Transient Recovery
30
LTC1702
1702fa
APPLICATIONS INFORMATION
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Making L smaller than this optimum value yields little or no
improvement in transient response. As the output voltage
recovers, the inductor current will briefly rise above the
level of the output current to replenish the charge lost from
the output capacitor. With a properly compensated loop,
the entire recovery time will be inside of 10µs.
Most loads care only about the maximum deviation from
ideal, which occurs somewhere in the first two cycles after
the load step hits. During this time, the output capacitor
does all the work until the inductor and control loop regain
control. The initial drop (or rise if the load steps down) is
entirely controlled by the ESR of the capacitor and amounts
to most of the total voltage drop. To minimize this drop,
reduce the ESR as much as possible by choosing low ESR
capacitors and/or paralleling multiple capacitors at the
output. The capacitance value accounts for the rest of the
voltage drop until the inductor current rises. With most
output capacitors, several devices paralleled to get the
ESR down will have so much capacitance that this drop
term is negligible. Ceramic capacitors are an exception; a
small ceramic capacitor can have suitably low ESR with
relatively small values of capacitance, making this second
drop term significant.
Optimizing Loop Compensation
Loop compensation has a fundamental impact on tran-
sient recovery time, the time it takes the LTC1702 to
recover after the output voltage has dropped due to output
capacitor ESR. Optimizing loop compensation entails
maintaining the highest possible loop bandwidth while
ensuring loop stability. The Feedback Component Selec-
tion section describes in detail how to design an optimized
feedback loop, appropriate for most LTC1702 systems.
Voltage Positioning
If the load transients consist primarily of load steps from
near zero load to full load and back, the transient response
can be traded off against DC regulation performance by
using a technique known as “voltage positioning.” The
goal is to intentionally compromise the DC regulation loop
such that the output rides near the maximum allowable
value (often +5%) with no load and near the minimum
allowable value at maximum load. With the load at zero,
any transient that comes along will be a current increase
which will cause the output voltage to fall. Since the output
voltage is initially at a high value, it can fall further before
LTC1702
FB
1702 F17a
1702 F17b
V
OUT
V
IN
+5%
–5%
NOM
MAX
0
V
OUT
LOAD
CURRENT
MAXIMUM
ALLOWABLE
TRANSIENT
Figure 17a. Standard Regulator Figure 17b. Standard Regulator—Transient Response
LTC1702
FB
1702 F17c
1702 F17d
V
OUT
V
IN
+5%
–5%
NOM
MAX
0
V
OUT
LOAD
CURRENT
Figure 17c. Voltage Positioning Regulator Figure 17d. Positioning Regulator—Transient Response
MAXIMUM
ALLOWABLE
TRANSIENT
≈2× FIGURE 17b
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LTC1702IGN#PBF

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Description:
Switching Voltage Regulators 2x 550kHz Sync 2-PhSw Reg Cntr
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