19
Bias Networks
One of the major advantages of the enhancement
mode technology is that it allows the designer to be
able to dc ground the source leads and then merely
apply a positive voltage on the gate to set the desired
amount of quiescent drain current Id.
Whereas a depletion mode PHEMT pulls maximum
drain current when V
gs
=0V, an enhancement mode
PHEMT pulls only a small amount of leakage current
when V
gs
=0V. Only when V
gs
is increased above V
th
, the
device threshold voltage, will drain current start to  ow.
At a V
ds
of 2.7V and a nominal V
gs
of 0.47V, the drain
current I
d
will be approximately 10 mA. The data sheet
suggests a minimum and maximum V
gs
over which the
desired amount of drain current will be achieved. It is
also important to note that if the gate terminal is left
open circuited, the device will pull some amount of
drain current due to leakage current creating a voltage
di erential between the gate and source terminals.
Passive Biasing
Passive biasing of the ATF-551M4 is accomplished by
the use of a voltage divider consisting of R1 and R2. The
voltage for the divider is derived from the drain voltage
which provides a form of voltage feedback through
the use of R3 to help keep drain current constant. In
the case of a typical depletion mode FET, the voltage
divider which is normally connected to a negative
voltage source is connected to the gate through
resistor R4. Additional resistance in the form of R5 (ap-
proximately 10KΩ) is added to provide current limiting
for the gate of enhancement mode devices such as
the ATF-551M4. This is especially important when the
device is driven to P1dB or Psat.
Resistor R3 is calculated based on desired V
ds
, I
ds
and
available power supply voltage.
V
DD
V
ds
I
ds
+ I
BB
R3 =
(1)
Figure 37. Typical ATF-551M4 LNA with Passive Biasing.
ATF-551M4 Applications Information
Introduction
The ATF-551M4 is a low noise enhancement mode
PHEMT designed for use in low cost commercial appli-
cations in the VHF through 10 GHz frequency range. As
opposed to a typical depletion mode PHEMT where the
gate must be made negative with respect to the source
for proper operation, an enhancement mode PHEMT
requires that the gate be made more positive than
the source for normal operation. Therefore a negative
power supply voltage is not required for an enhance-
ment mode device. Biasing an enhancement mode
PHEMT is much like biasing the typical bipolar junction
transistor. Instead of a 0.7V base to emitter voltage,
the ATF-551M4 enhancement mode PHEMT requires a
nominal 0.47V potential between the gate and source
for a nominal drain current of 10 mA.
Matching Networks
The techniques for impedance matching an en-
hancement mode device are very similar to those for
matching a depletion mode device. The only di erence
is in the method of supplying gate bias. S and Noise
Parameters for various bias conditions are listed in
this data sheet. The circuit shown in Figure 37 shows a
typical LNA circuit normally used for 900 and 1900 MHz
applications. Consult the Broadcom web site for appli-
cation notes covering speci c designs and applications.
High pass impedance matching networks consisting
of L1/C1 and L4/C4 provide the appropriate match for
noise  gure, gain, S11 and S22. The high pass structure
also provides low frequency gain reduction which can
be bene cial from the standpoint of improving out-of-
band rejection.
Capacitors C2 and C5 provide a low impedance in-band
RF bypass for the matching networks. Resistors R3 and
R4 provide a very important low frequency termination
for the device. The resistive termination improves low
frequency stability. Capacitors C3 and C6 provide the
RF bypass for resistors R3 and R4. Their value should be
chosen carefully as C3 and C6 also provide a termina-
tion for low frequency mixing products. These mixing
products are as a result of two or more in-band signals
mixing and producing third order in-band distor-
tion products. The low frequency or di erence mixing
products are terminated by C3 and C6. For best sup-
pression of third order distortion products based on
the CDMA 1.25 MHz signal spacing, C3 and C6 should
be 0.1 uF in value. Smaller values of capacitance will
not suppress the generation of the 1.25 MHz di erence
signal and as a result will show up as poorer two tone
IP3 results.
INPUT
C1
C2
C3
L1
R4
R1 R2
Vdd
R3
L2 L3
L4
Q1
Zo
Zo
C4
C5
C6
OUTPUT
R5
20
V
DD
is the power supply voltage.
V
ds
is the device drain to source voltage.
I
ds
is the desired drain current.
I
BB
is the current  owing through the R1/R2 resistor
voltage divider network.
The value of resistors R1 and R2 are calculated with the
following formulas.
V
gs
p
I
BB
R1 =
(2)
R2 =
(V
ds
V
gs
) R1
gs
(3)
Example Circuit
V
DD
= 3V
V
ds
= 2.7V
I
ds
= 10 mA
V
gs
= 0.47V
Choose I
BB
to be at least 10X the maximum expected
gate leakage current. I
BB
was conservatively chosen to
be 0.5 mA for this example. Using equations (1), (2), and
(3) the resistors are calculated as follows
R1 = 940Ω
R2 = 4460Ω
R3 = 28.6Ω
Active Biasing
Active biasing provides a means of keeping the
quiescent bias point constant over temperature and
constant over lot to lot variations in device dc perfor-
mance. The advantage of the active biasing of an en-
hancement mode PHEMT versus a depletion mode
PHEMT is that a negative power source is not required.
The techniques of active biasing an enhancement
mode device are very similar to those used to bias a
bipolar junction transistor. An active bias scheme is
shown in Figure 38.
R1 and R2 provide a constant voltage source at the
base of a PNP transistor at Q2. The constant voltage
at the base of Q2 is raised by 0.7 volts at the emitter.
The constant emitter voltage plus the regulated V
DD
supply are present across resistor R3. Constant voltage
across R3 provides a constant current supply for the
drain current. Resistors R1 and R2 are used to set the
desired V
ds
. The combined series value of these resistors
also sets the amount of extra current consumed by the
bias network. The equations that describe the circuits
operation are as follows.
Rearranging equation (4)provides the following formula
and rearranging equation (5) provides the follow
formula
V
E
= V
ds
+ (I
ds
R4) (1)
R3 = V
DD
V
E
(2)
p
I
ds
V
B
= V
E
V
BE
(3)
V
B
= R1 V
DD
(4)
p
R1 + R2
V
DD
= I
BB
(R1 + R2)
R
1
(V
DD
V
B
)
p
V
B
R1 =
V
DD
(5A)
9
I
BB
(
V
DD
V
B
)
p
V
B
(5)
(4A)
R2 =
1 +
Figure 38. Typical ATF-551M4 LNA with Active Biasing.
INPUT
C1
C2
C3
C7
L1
R5
R6
R7 R3
R2
R1
Q2
Vdd
R4
L2 L3
L4
Q1
Zo
Zo
C4
C5
C6
OUTPUT
Example Circuit
V
DD
= 3 V, V
ds
= 2.7 V, I
ds
= 10 mA, R4 = 10Ω, V
BE
= 0.7V
Equation (1) calculates the required voltage at the
emitter of the PNP transistor based on desired V
ds
and
I
ds
through resistor R4 to be 2.8V. Equation (2) calcu-
lates the value of resistor R3 which determines the
drain current I
ds
. In the example R3=18.2Ω. Equation
(3) calculates the voltage required at the junction of
resistors R1 and R2. This voltage plus the step-up of
the base emitter junction determines the regulated
V
ds
. Equations (4) and (5) are solved simultaneously
to determine the value of resistors R1 and R2. In the
example R1 = 4200Ω and R2 =1800Ω.
21
ATF-551M4 Die Model
GATE
SOURCE
INSIDE Package
Port
G
Num=1
C
C1
C=0.28 pF
Port
S1
Num=2
SOURCE
DRAIN
Port
S2
Num=4
Port
D
Num=3
L
L6
L=0.147 nH
R=0.001
C
C2
C=0.046 pF
L
L7
L=0.234 nH
R=0.001
MSub
TLINP
TL3
Z=Z2 Ohm
L=23.6 mil
K=K
A=0.000
F=1 GHz
TanD=0.001
TLINP
TL9
Z=Z2 Ohm
L=11 mil
K=K
A=0.000
F=1 GHz
TanD=0.001
VAR
VAR1
K=5
Z2=85
Z1=30
Var
Egn
TLINP
TL1
Z=Z2/2 Ohm
L=22 mil
K=K
A=0.000
F=1 GHz
TanD=0.001
TLINP
TL2
Z=Z2/2 Ohm
L=20 0 mil
K=K
A=0.000
F=1 GHz
TanD=0.001
TLINP
TL7
Z=Z2/2 Ohm
L=5.2 mil
K=K
A=0.000
F=1 GHz
TanD=0.001
TLINP
TL5
Z=Z2 Ohm
L=27.5 mil
K=K
A=0.000
F=1 GHz
TanD=0.001
L
L1
L=0.234 nH
R=0.001
L
L4
L=0.281 nH
R=0.001
GaAsFET
FET1
Mode1=MESFETM1
Mode=Nonlinear
MSUB
MSub2
H=25.0 mil
Er=9.6
Mur=1
Cond=1.0E+50
Hu=3.9e+034 mil
T=0.15 mil
TanD=0
Rough=0 mil
ATF-551M4 Minipak Model
NFET=yes
PFET=no
Vto=0.3
Beta=0.444
Lambda=72e-3
Alpha=13
Tau=
Tnom=16.85
Idstc=
Ucrit=-0.72
Vgexp=1.91
Gamds=1e-4
Vtotc=
Betatce=
Rgs=0.5 Ohm
Rf=
Gscap=2
Cgs=0.6193 pF
Cgd=0.1435 pF
Gdcap=2
Fc=0.65
Rgd=0.5 Ohm
Rd=2.025 Ohm
Rg=1.7 Ohm
Rs=0.675 Ohm
Ld=
Lg=0.094 nH
Ls=
Cds=0.100 pF
Rc=390 Ohm
Crf=0.1 F
Gsfwd=
Gsrev=
Gdfwd=
Gdrev=
R1=
R2=
Vbi=0.95
Vbr=
Vjr=
Is=
Ir=
Imax=
Xti=
Eg=
N=
Fnc=1 MHz
R=0.08
P=0.2
C=0.1
Taumdl=no
wVgfwd=
wBvgs=
wBvgd=
wBvds=
wldsmax=
wPmax=
AllParams=
Advanced_Curtice2_Model
MESFETM1
R7 is chosen to be 1 kΩ. This resistor keeps a small
amount of current  owing through Q2 to help maintain
bias stability. R6 is chosen to be 10 KΩ. This value of re-
sistance is high enough to limit Q1 gate current in the
presence of high RF drive levels as experienced when
Q1 is driven to the P1dB gain compression point. C7
provides a low frequency bypass to keep noise from Q2
e ecting the operation of Q1. C7 is typically 0.1 μF.
Maximum Suggested Gate Current
The maximum suggested gate current for the
ATF-551M4 is 1 mA. Incorporating resistor R5 in the
passive bias network or resistor R6 in the active bias
network safely limits gate current to 500 μA at P1dB
drive levels. In order to minimize component count in
the passive biased ampli er circuit, the 3 resistor bias
circuit consisting of R1, R2, and R5 can be simpli ed
if desired. R5 can be removed if R1 is replaced with a
5.6KΩ resistor and if R2 is replaced with a 27KΩ resistor.
This combination should limit gate current to a safe
level.

ATF-551M4-TR1

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
RF JFET Transistors Transistor GaAs Single Voltage
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet