PRELIMINARY
8-Mbit (1M x 8) Static RAM
CY7C1059DV33
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-00061 Rev. *B Revised July 21, 2006
Features
•High speed
—t
AA
= 10 ns
• Low active power
—I
CC
= 110 mA
• Low CMOS standby power
—I
SB2
= 20 mA
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
and OE features
• Available in lead-free 36-ball FBGA and 44-pin TSOP II
ZS44 packages
Functional Description
[1]
The CY7C1059DV33 is a high-performance CMOS Static
RAM organized as 1M words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE
), and tri-state drivers. Writing
to the device is accomplished by taking Chip Enable (CE
) and
Write Enable (WE
) inputs LOW. Data on the eight I/O pins (I/O
0
through I/O
7
) is then written into the location specified on the
address pins (A
0
through A
19
).
Reading from the device is accomplished by taking Chip
Enable (CE
) and Output Enable (OE) LOW while forcing Write
Enable (WE
) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE
LOW, and WE LOW).
The CY7C1059DV33 is available in 36-ball FBGA and 44-pin
TSOP II package with center power and ground (revolutionary)
pinout.
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
14
15
Logic Block Diagram
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
1M x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
11
A
13
A
12
A
CE
A
A
16
A
17
A
9
A
18
A
10
A
19
