PRELIMINARY
CY7C1059DV33
Document #: 001-00061 Rev. *B Page 4 of 9
AC Test Loads and Waveforms
[4]
AC Switching Characteristics
[5]
Over the Operating Range
Parameter Description
–10
UnitMin. Max.
Read Cycle
t
power
[6]
V
CC
(typical) to the first access 100 µs
t
RC
Read Cycle Time 10 ns
t
AA
Address to Data Valid 10 ns
t
OHA
Data Hold from Address Change 3 ns
t
ACE
CE LOW to Data Valid 10 ns
t
DOE
OE LOW to Data Valid 5 ns
t
LZOE
OE LOW to Low-Z 0 ns
t
HZOE
OE HIGH to High-Z
[7, 8]
5ns
t
LZCE
CE LOW to Low-Z
[8]
3ns
t
HZCE
CE HIGH to High-Z
[7, 8]
5ns
t
PU
CE LOW to Power-up 0 ns
t
PD
CE HIGH to Power-down 10 ns
Write Cycle
[9, 10]
t
WC
Write Cycle Time 10 ns
t
SCE
CE LOW to Write End 7 ns
t
AW
Address Set-up to Write End 7 ns
t
HA
Address Hold from Write End 0 ns
t
SA
Address Set-up to Write Start 0 ns
t
PWE
WE Pulse Width 7 ns
t
SD
Data Set-up to Write End 5 ns
t
HD
Data Hold from Write End 0 ns
t
LZWE
WE HIGH to Low-Z
[8]
3ns
t
HZWE
WE LOW to High-Z
[7, 8]
5ns
Notes:
4. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. t
POWER
gives the minimum amount of time that the power supply should be at stable, typical V
CC
values until the first memory access can be performed.
7. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured when the outputs enter a high impedance state.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9. The internal Write time of the memory is defined by the overlap of CE
LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of
these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
10.The minimum Write cycle time for Write Cycle No. 3 (WE
controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
Rise Time: 1 V/ns
Fall Time: 1 V/ns
30 pF*
OUTPUT
Z = 50Ω
50Ω
1.5V
(b)
(a)
3.3V
OUTPUT
5 pF
(c)
R 317Ω
R2
351Ω
High-Z characteristics:
