XA7S25-1CSGA324Q Datasheet XA7S25-2CSGA225I, XA7S25-1CSGA225Q, XA7S25-2CSGA324I | P1-P3

DS171 (v1.0) March 14, 2017 www.xilinx.com

Product Specification 1

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General Description

The Xilinx Automotive (XA) Spartan®-7 family of FPGAs, using the high-K metal gate (HKMG) process, provides the best combination of

high performance and low power to service a wide variety of automotive applications. XA Spartan-7 FPGAs use the same 28HPL process

as the established 7 series families and benefit from many of the same underlying architectural elements. The result is a family of compact,

cost-optimized FPGAs that provide high logic and I/O performance with strictly controlled power consumption that are able to fit into

aggressively small form factor packaging—all at a low cost.

The six-member family delivers expanded densities ranging from 6,000 to 102,400 logic cells and faster, more comprehensive

connectivity. The XA Spartan-7 family offers a new, more efficient, dual-register 6-input look-up table (LUT) logic and a rich selection of

built-in system-level blocks. These include 36Kb (2 x 18Kb) block RAMs with built-in FIFO logic for on-chip data buffering, DSP slices with

25 x 18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized symmetric coefficient filtering,

enhanced mixed-mode clock management blocks, SelectIO™ technology with support of DDR3 interfacing up to 800Mb/s, advanced

system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA

protection. These features provide a low-cost programmable alternative to custom ASIC products with unprecedented ease of use.

XA Spartan-7 FPGAs offer the best solution for flexible and scalable high-volume logic designs, high-bandwidth parallel DSP processing

designs, and cost-sensitive applications where multiple interfacing standards are required.

Summary of XA Spartan-7 FPGA Features

• Automotive Temperatures:

• I-Grade: T

= –40°C to +100°C

• Q-Grade: T

= –40°C to +125°C

• Automotive Standards:

• Xilinx is ISO-TS16949 compliant

• AEC-Q100 qualification

• Production Part Approval Process (PPAP) documentation

• Beyond AEC-Q100 qualification is available upon request

• Designed for low cost

• Multiple efficient integrated blocks

• Optimized selection of I/O standards

• High-volume plastic wire-bonded packages

• Low static and dynamic power

• 28 nm process optimized for cost and low power

• High-performance SelectIO technology with support for DDR3

• Up to 1250 Mb/s data transfer rate per differential I/O

• Selectable output drive, up to 24mA per pin

• 3.3V to 1.2V I/O standards and protocols

• Low-cost HSTL and SSTL memory interfaces

• Adjustable I/O slew rates to improve signal integrity

• Efficient DSP slices

• High-performance arithmetic and signal processing

• Fast 25 x 18 multiplier and 48-bit accumulator

• Pipelining and cascading capability

• Pre-adder to assist filter applications

• Integrated Memory Controller blocks

• DDR, DDR2, DDR3, and LPDDR support

• Data rates up to 800Mb/s

• Multi-port bus structure with independent FIFO to reduce

design timing issues

• Abundant logic resources with increased logic capacity

• Optional shift register or distributed RAM support

• Efficient 6-input LUTs improve performance and minimize

power

• LUT with dual flip-flops for pipeline centric applications

• Block RAM with a wide range of granularity

• Fast block RAM with byte write enable

• 36Kb blocks that can be optionally programmed as two

independent 18Kb block RAMs

• Clock Management Tile (CMT) for enhanced performance

• Low noise, flexible clocking

• Digital Clock Managers (DCMs) eliminate clock skew and

duty cycle distortion

• Phase-Locked Loops (PLLs) for low-jitter clocking

• Frequency synthesis with simultaneous multiplication,

division, and phase shifting

• 32 low-skew global clock networks

• Simplified configuration supports low-cost standards:

• 2-pin auto-detect configuration

• Broad third-party SPI (up to x4) flash support

• Multi-boot support for remote upgrade with multiple

bitstreams, using watchdog protection

• Enhanced security for design protection.

• Unique Device DNA identifier for design authentication

• Wide variety of configuration options, including support for

commodity memories, 256-bit AES encryption with HMAC/SHA-

256 authentication, and built-in SEU detection and correction

• Industry-leading IP and reference designs

• Strong automotive-specific third-party ecosystem with IP,

development boards, and design services

XA Spartan-7 Automotive FPGA

Data Sheet: Overview

DS171 (v1.0) March 14, 2017 Product Specification

Data Sheet: Overview

DS171 (v1.0) March 14, 2017 www.xilinx.com

Product Specification 2

XA Spartan-7 FPGA Feature Summary

FPGA Device Package Combinations and Available I/Os

CLBs, Slices, and LUTs

Some key features of the CLB architecture include:

• Real 6-input look-up tables (LUTs)

• Memory capability within the LUT

• Register and shift register functionality

The LUTs in XA Spartan-7 FPGAs can be configured as either one 6-input LUT (64-bit ROMs) with one output, or as two 5-

input LUTs (32-bit ROMs) with separate outputs but common addresses or logic inputs. Each LUT output can optionally be

registered in a flip-flop. Four such LUTs and their eight flip-flops as well as multiplexers and arithmetic carry logic form a

slice, and two slices form a configurable logic block (CLB). Four of the eight flip-flops per slice (one per LUT) can optionally

be configured as latches.

Between 25–50% of all slices can also use their LUTs as distributed 64-bit RAM or as 32-bit shift registers (SRL32) or as two

SRL16s. Modern synthesis tools take advantage of these highly efficient logic, arithmetic, and memory features.

Table 1: XA Spartan-7 FPGA Feature Summary by Device

Device

Logic

Cells

CLB

DSP

Slices

(2)

Block RAM Blocks

(3)

CMTs

(4)

PCIe GT

XADC

Blocks

Total I/O

Banks

(5)

Max User

I/O

Slices

(1)

Max Distrib-

uted RAM

(Kb)

18Kb 36Kb

Max

(Kb)

XA7S6 6,000 938 70 10 10 5 180 2 0 0 0 2 100

XA7S15 12,800 2,000 150 20 20 10 360 2 0 0 0 2 100

XA7S25 23,360 3,650 313 80 90 45 1,620 3 0 0 1 3 150

XA7S50 52,160 8,150 600 120 150 75 2,700 5 0 0 1 5 250

XA7S75 76,800 12,000 832 140 180 90 3,240 8 0 0 1 8 400

XA7S100 102,400 16,000 1,110 160 240 120 4,320 8 0 0 1 8 400

Notes:

1. Each 7 series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.

2. Each DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an accumulator.

3. Block RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18Kb blocks.

4. Each CMT contains one MMCM and one PLL.

5. Does not include configuration Bank 0.

Table 2: XA Spartan-7 FPGA Device-Package Combinations and Maximum I/Os

Package CPGA196 CSGA225 CSGA324 FTGB196 FGGA484 FGGA676

Size (mm) 8 x 8 13 x 13 15 x 15 15 x 15 23 x 23 27 x 27

Ball Pitch (mm)0.50.80.81.01.01.0

Device HR I/O

(1)

HR I/O

(1)

HR I/O

(1)

HR I/O

(1)

HR I/O

(1)

HR I/O

(1)

XA7S6 100 100 100

XA7S15 100 100 100

XA7S25 150 150 100

XA7S50 210 100 250

XA7S75 338 400

XA7S100

338 400

Notes:

1. HR = High-range I/O with support for I/O voltage from 1.2V to 3.3V.

Data Sheet: Overview

DS171 (v1.0) March 14, 2017 www.xilinx.com

Product Specification 3

Clock Management

Some of the key highlights of the clock management architecture include:

• High-speed buffers and routing for low-skew clock distribution

• Frequency synthesis and phase shifting

• Low-jitter clock generation and jitter filtering

Each XA Spartan-7 FPGA has up to 8 clock management tiles (CMTs), each consisting of one mixed-mode clock manager

(MMCM) and one phase-locked loop (PLL).

Mixed-Mode Clock Manager and Phase-Locked Loop

The MMCM and PLL share many characteristics. Both can serve as a frequency synthesizer for a wide range of frequencies

and as a jitter filter for incoming clocks. At the center of both components is a voltage-controlled oscillator (VCO), which

speeds up and slows down depending on the input voltage it receives from the phase frequency detector (PFD).

There are three sets of programmable frequency dividers: D, M, and O. The pre-divider D (programmable by configuration

and afterwards via DRP) reduces the input frequency and feeds one input of the traditional PLL phase/frequency

comparator. The feedback divider M (programmable by configuration and afterwards via DRP) acts as a multiplier because

it divides the VCO output frequency before feeding the other input of the phase comparator. D and M must be chosen

appropriately to keep the VCO within its specified frequency range. The VCO has eight equally-spaced output phases

(0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). Each can be selected to drive one of the output dividers (six for the PLL,

O0 to O5, and seven for the MMCM, O0 to O6), each programmable by configuration to divide by any integer from 1 to 128.

The MMCM and PLL have three input-jitter filter options: low bandwidth, high bandwidth, or optimized mode. Low-bandwidth

mode has the best jitter attenuation but not the smallest phase offset. High-bandwidth mode has the best phase offset, but

not the best jitter attenuation. Optimized mode allows the tools to find the best setting.

MMCM Additional Programmable Features

The MMCM can have a fractional counter in either the feedback path (acting as a multiplier) or in one output path. Fractional

counters allow non-integer increments of

/8 and can thus increase frequency synthesis capabilities by a factor of 8.

The MMCM can also provide fixed or dynamic phase shift in small increments that depend on the VCO frequency. At

1,440MHz, the phase-shift timing increment is 13ps.

Clock Distribution

Each XA Spartan-7 FPGA provides six different types of clock lines (BUFG, BUFR, BUFIO, BUFH, BUFMR, and the high-

performance clock) to address the different clocking requirements of high fanout, short propagation delay, and extremely low

skew.

Global Clock Lines

In each XA Spartan-7 FPGA (except XA7S6 and XA7S15), 32 global clock lines have the highest fanout and can reach

every flip-flop clock, clock enable, and set/reset, as well as many logic inputs. There are 12 global clock lines within any clock

region driven by the horizontal clock buffers (BUFH). Each BUFH can be independently enabled/disabled, allowing for clocks

to be turned off within a region, thereby offering fine-grain control over which clock regions consume power. Global clock

lines can be driven by global clock buffers, which can also perform glitchless clock multiplexing and clock enable functions.

Global clocks are often driven from the CMT, which can completely eliminate the basic clock distribution delay.

Regional Clocks

Regional clocks can drive all clock destinations in their region. A region is defined as an area that is 50 I/O and 50 CLB high

and half the chip wide. XA Spartan-7 FPGAs have between two and eight regions. There are four regional clock tracks in

every region. Each regional clock buffer can be driven from any of four clock-capable input pins, and its frequency can

optionally be divided by any integer from 1 to 8.

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XA7S25-1CSGA324Q

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FPGA - Field Programmable Gate Array XA7S25-1CSGA324Q

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XA7S25-1CSGA324Q

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