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XA7S25-1CSGA324Q

P1-P3P4-P6P7-P9
Data Sheet: Overview
DS171 (v1.0) March 14, 2017 www.xilinx.com
Product Specification 4
I/O Clocks
I/O clocks are especially fast and serve only I/O logic and serializer/deserializer (SerDes) circuits, as described in the
I/O Logic section. The XA Spartan-7 devices have a direct connection from the MMCM to the I/O for low-jitter, high-
performance interfaces.
Block RAM
Some of the key features of the block RAM include:
• Dual-port 36Kb block RAM with port widths of up to 72
• Programmable FIFO logic
• Built-in optional error correction circuitry
Every XA Spartan-7 FPGA has between 5 and 120 dual-port block RAMs, each storing 36Kb. Each block RAM has two
completely independent ports that share nothing but the stored data.
Synchronous Operation
Each memory access, read or write, is controlled by the clock. All inputs, data, address, clock enables, and write enables are
registered. Nothing happens without a clock. The input address is always clocked, retaining data until the next operation. An
optional output data pipeline register allows higher clock rates at the cost of an extra cycle of latency.
During a write operation, the data output can reflect either the previously stored data, the newly written data, or can remain
unchanged.
Programmable Data Width
Each port can be configured as 32K × 1, 16K × 2, 8K × 4, 4K × 9 (or 8), 2K × 18 (or 16), 1K × 36 (or 32), or 512 × 72 (or 64).
The two ports can have different aspect ratios without any constraints.
Each block RAM can be divided into two completely independent 18Kb block RAMs that can each be configured to any
aspect ratio from 16K × 1 to 512 × 36. Everything described previously for the full 36Kb block RAM also applies to each of
the smaller 18Kb block RAMs.
Only in simple dual-port (SDP) mode can data widths of greater than 18 bits (18Kb RAM) or 36 bits (36Kb RAM) be
accessed. In this mode, one port is dedicated to read operation, the other to write operation. In SDP mode, one side (read
or write) can be variable, while the other is fixed to 32/36 or 64/72.
Both sides of the dual-port 36Kb RAM can be of variable width.
Two adjacent 36Kb block RAMs can be configured as one cascaded 64K × 1 dual-port RAM without any additional logic.
Error Detection and Correction
Each 64-bit-wide block RAM can generate, store, and utilize eight additional Hamming code bits and perform single-bit error
correction and double-bit error detection (ECC) during the read process. The ECC logic can also be used when writing to or
reading from external 64- to 72-bit-wide memories.
FIFO Controller
The built-in FIFO controller for single-clock (synchronous) or dual-clock (asynchronous or multi-rate) operation increments
the internal addresses and provides four handshaking flags: full, empty, almost full, and almost empty. The almost full and
almost empty flags are freely programmable. Similar to the block RAM, the FIFO width and depth are programmable, but the
write and read ports always have identical width.
First word fall-through mode presents the first-written word on the data output even before the first read operation. After the
first word has been read, there is no difference between this mode and the standard mode.
Data Sheet: Overview
DS171 (v1.0) March 14, 2017 www.xilinx.com
Product Specification 5
Digital Signal Processing — DSP Slice
Some highlights of the DSP functionality include:
• 25 × 18 twos complement multiplier/accumulator high-resolution (48 bit) signal processor
• Power saving pre-adder to optimize symmetrical filter applications
• Advanced features: optional pipelining, optional ALU, and dedicated buses for cascading
DSP applications use many binary multipliers and accumulators, best implemented in dedicated DSP slices. All 7 series
FPGAs have many dedicated, full custom, low-power DSP slices, combining high speed with small size while retaining
system design flexibility.
Each DSP slice fundamentally consists of a dedicated 25 × 18 bit two's complement multiplier and a 48-bit accumulator,
both capable of operating up to 550MHz. The multiplier can be dynamically bypassed, and two 48-bit inputs can feed a
single-instruction-multiple-data (SIMD) arithmetic unit (dual 24-bit add/subtract/accumulate or quad 12-bit
add/subtract/accumulate), or a logic unit that can generate any one of ten different logic functions of the two operands.
The DSP includes an additional pre-adder, typically used in symmetrical filters. This pre-adder improves performance in
densely packed designs and reduces the DSP slice count by up to 50%. The DSP also includes a 48-bit-wide Pattern
Detector that can be used for convergent or symmetric rounding. The pattern detector is also capable of implementing
96-bit-wide logic functions when used in conjunction with the logic unit.
The DSP slice provides extensive pipelining and extension capabilities that enhance the speed and efficiency of many
applications beyond digital signal processing, such as wide dynamic bus shifters, memory address generators, wide bus
multiplexers, and memory-mapped I/O register files. The accumulator can also be used as a synchronous up/down counter.
Input/Output
Some highlights of the input/output functionality include:
• High-performance SelectIO technology with support for 800Mb/s DDR3
• Digitally Controlled Impedance that can be 3-stated for lowest power, high-speed I/O operation
The number of I/O pins varies depending on device and package size. Each I/O is configurable and can comply with a large
number of I/O standards. With the exception of the supply pins and a few dedicated configuration pins, all other package pins
have the same I/O capabilities, constrained only by certain banking rules. The I/O in XA Spartan-7 FPGAs are classed as
high range (HR). HR I/Os offer a wide range of voltage support, from 1.2V to 3.3V.
HR I/O pins in XA Spartan-7 FPGAs are organized in banks, with 50 pins per bank. Each bank has one common V
CCO
output supply, which also powers certain input buffers. Some single-ended input buffers require an internally generated or an
externally applied reference voltage (V
REF
). There are two V
REF
pins per bank (except configuration bank 0). A single bank
can have only one V
REF
voltage value.
XA Spartan-7 FPGAs use small form factor wire-bond packages for lowest cost.
I/O Electrical Characteristics
Single-ended outputs use a conventional CMOS push/pull output structure driving High towards V
CCO
or Low towards
ground, and can be put into a high-Z state. The system designer can specify the slew rate and the output strength. The input
is always active but is usually ignored while the output is active. Each pin can optionally have a weak pull-up or a weak pull-
down resistor.
Most signal pin pairs can be configured as differential input pairs or output pairs. Differential input pin pairs can optionally be
terminated with a 100Ω internal resistor. All XA Spartan-7 devices support differential standards beyond LVDS: RSDS,
BLVDS, differential SSTL, and differential HSTL.
Each of the I/Os supports memory I/O standards, such as single-ended and differential HSTL as well as single-ended SSTL
and differential SSTL. The SSTL I/O standard can support data rates of up to 800Mb/s for DDR3 interfacing applications.
Data Sheet: Overview
DS171 (v1.0) March 14, 2017 www.xilinx.com
Product Specification 6
Low Power I/O Features
The I/Os have low power modes for IBUF and IDELAY to provide further power savings, especially when used to implement
memory interfaces.
I/O Logic
Input Delay
All inputs can be configured as either combinatorial or registered. Double data rate (DDR) is supported by all inputs and
outputs. Any input can be individually delayed by up to 32 increments of 78ps, 52ps, or 39ps each. Such delays are
implemented as IDELAY. The number of delay steps can be set by configuration and can also be incremented or
decremented while in use.
ISERDES and OSERDES
Many applications combine high-speed, bit-serial I/O with slower parallel operation inside the device. This requires a
serializer and deserializer (SerDes) inside the I/O structure. Each I/O pin possesses an 8-bit IOSERDES (ISERDES and
OSERDES) capable of performing serial-to-parallel or parallel-to-serial conversions with programmable widths of 2, 3, 4, 5,
6, 7, or 8 bits. By cascading two IOSERDES from two adjacent pins (default from differential I/O), wider width conversions
of 10 and 14 bits can also be supported. The ISERDES has a special oversampling mode capable of asynchronous data
recovery for applications like a 1.25Gb/s LVDS I/O-based SGMII interface.
Configuration
There are many advanced configuration features, including:
• High-speed SPI configuration
• Built-in multi-boot and safe-update capability
• 256-bit AES encryption with HMAC/SHA-256 authentication
• Built-in SEU detection and correction
• Partial reconfiguration
XA Spartan-7 FPGAs store their customized configuration in SRAM-type internal latches. There are up to 30Mb
configuration bits, depending on device size and user-design implementation options. The configuration storage is volatile
and must be reloaded whenever the FPGA is powered up. This storage can also be reloaded at any time by pulling the
PROGRAM_B pin Low. Several methods and data formats for loading configuration are available, determined by the three
mode pins.
The SPI interface (x1, x2, and x4 modes) is a common method used for configuring the FPGA. Users can directly connect
an SPI flash to the FPGA, and the FPGA's internal configuration logic reads the bitstream out of the flash and configures
itself. The FPGA automatically detects the bus width on the fly, eliminating the need for any external controls or switches.
Bus widths supported are x1, x2, and x4 for SPI. The larger bus widths increase configuration speed and reduce the amount
of time it takes for the FPGA to start up after power-on. Refer to UG470
, 7 Series FPGAs Configuration User Guide for
details.
In master mode, the FPGA can drive the configuration clock from an internally generated clock, or for higher speed
configuration, the FPGA can use an external configuration clock source. This allows high-speed configuration with the ease
of use characteristic of master mode. Slave modes up to 32 bits wide are also supported by the FPGA that are especially
useful for processor-driven configuration.
The FPGA has the ability to reconfigure itself with a different image using SPI flash, eliminating the need for an external
controller. The FPGA can reload its original design in case there are any errors in the data transmission, ensuring an
operational FPGA at the end of the process. This is especially useful for updates to a design after the end product has been
shipped. Customers can ship their products with an early version of the design, thus getting their products to market faster.
This feature allows customers to keep their end users current with the most up-to-date designs while the product is already
in the field.
P1-P3P4-P6P7-P9

XA7S25-1CSGA324Q

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FPGA - Field Programmable Gate Array XA7S25-1CSGA324Q
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