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HIP6602BCBZ-T

P1-P3P4-P6P7-P9P10-P12P13-P13
10
FN9076.6
December 3, 2015
FIGURE 4. 3nF LOADING PROFILE FIGURE 5. POWER DISSIPATION vs LOADING
FIGURE 6. POWER DISSIPATION vs FREQUENCY, PVCC = 5V FIGURE 7. POWER DISSIPATION vs FREQUENCY, PVCC = 5V
Typical Performance Curves (Continued)
1200
800
600
400
200
0
0 500 1000
FREQUENCY (kHz)
POWER (mW)
1500
PVCC = VCC = 12V
1000
C
U
= C
L
= 3nF
C
L
= 3nF, C
U
= 0nF
C
U
= 3nF, C
L
= 0nF
10kHz
30kHz
100kHz
200kHz
500kHz
12 345
1200
1000
800
600
400
200
0
POWER (mW)
GATE CAPACITANCE (C
U
= C
L
), (nF)
PVCC = VCC = 12V
PVCC = 5V, VCC = 12V
C
U
= C
L
= 4nF
C
U
= C
L
= 5nF
C
U
= C
L
= 2nF
C
U
= C
L
=1nF
800
700
500
600
300
100
0
0 500 1500 2000
FREQUENCY (kHz)
POWER (mW)
1000
200
400
C
U
= C
L
= 3nF
0 500 1000 1500 2000
FREQUENCY (kHz)
350
300
250
200
150
100
50
0
POWER (mW)
PVCC = 5V, VCC = 12V
C
L
= 1nF, C
U
= 0nF
C
U
= C
L
= 1nF
C
U
= 1nF, C
L
= 0nF
HIP6602B
11
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9076.6
December 3, 2015
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
FIGURE 8. POWER DISSIPATION vs LOADING, PVCC = 5V
Typical Performance Curves (Continued)
30kHz
100kHz
200kHz
500kHz
1MHz
2MHz
1.5MHz
PVCC = 5V,
VCC = 12V
54321
POWER (mW)
600
500
400
300
200
100
0
GATE CAPACITANCE (C
U
= C
L
), (nF)
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE REVISION CHANGE
December 3, 2015 FN9076.6 Added recommended replacement parts ISL6622 and ISL6625A.
Added Rev History and About Intersil Verbiage.
Updated POD M14.15 to most current version. Rev change as follows:
Added land pattern and moved dimensions from table onto drawing.
HIP6602B
12
FN9076.6
December 3, 2015
HIP6602B
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.5x5
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHB ISSUE C)
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.80 0.90 1.00 -
A1 - - 0.05 -
A2 - - 1.00 9
A3 0.20 REF 9
b 0.28 0.33 0.40 5, 8
D 5.00 BSC -
D1 4.75 BSC 9
D2 2.55 2.70 2.85 7, 8
E 5.00 BSC -
E1 4.75 BSC 9
E2 2.55 2.70 2.85 7, 8
e 0.80 BSC -
k0.25 - - -
L 0.35 0.60 0.75 8
L1 - - 0.15 10
N162
Nd 4 3
Ne 4 4 3
P- -0.609
--129
Rev. 2 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
P1-P3P4-P6P7-P9P10-P12P13-P13

HIP6602BCBZ-T

Mfr. #:
Buy HIP6602BCBZ-T
Manufacturer:
Renesas / Intersil
Description:
Gate Drivers LD VER OF HI6602BCB-
Lifecycle:
New from this manufacturer.
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