AD7888ARUZ-REEL7 Datasheet AD7888ARUZ-REEL7, AD7888ARUZ, AD7888ARZ | P13-P15

AD7888

–12–

CS and the second rising edge of SCLK as shown in Figure 14a.

In microcontroller applications, this is readily achievable by

driving the CS input from one of the port lines and ensuring

that the serial data read (from the microcontrollers serial port) is

not initiated for 5 µs. In DSP applications, where the CS is

generally derived from the serial frame synchronization line, it is

not possible to separate the first falling edge and second rising

edge of SCLK after the CS falling edge by up to 5 µs. There-

fore, the user will need to write to the Control Register to exit

this mode and (by writing PM1 = 0 and PM0 = 0) put the part

into normal mode. A second conversion will then need to be

initiated when the part is powered up to obtain a conversion

result as shown in Figure 14b.

SCLK

4 LEADING ZEROES

+ CONVERSION RESULT

DOUT

DATA INDIN

168

4 LEADING ZEROES

+ CONVERSION RESULT

DATA IN

168

4 LEADING ZEROES

+ CONVERSION RESULT

DATA IN

116

PM1 AND PM0 = 0 TO PLACE

THE PART IN NORMAL MODE

PM1 = 1 AND PM0 = 0 TO

PLACE THE PART BACK IN

AUTOSHUTDOWN MODE

CONTROL REGISTER DATA IS LOADED ON

THE FIRST 8 CLOCKS. PM1 = 1 AND PM0 = 0

THE PART ENTERS

SHUTDOWN AT THE END

OF CONVERSION AS

PM1 = 1 AND PM0 = 0

THE PART REMAINS POWERED

UP AS PM1 AND PM0 = 0

THE PART BEGINS TO POWER-

UP FROM SHUTDOWN

THE PART ENTERS

SHUTDOWN AT THE END OF

CONVERSION AS PM1 = 1

AND PM0 = 0

Figure 14b. Autoshutdown Operation

SCLK

4 LEADING ZEROES + CONVERSION RESULT

DOUT

DATA IN

DIN

CONTROL REGISTER DATA IS LOADED ON

THE FIRST 8 CLOCKS. PM1 = 1 AND PM0 = 1

4 LEADING ZEROES + CONVERSION RESULT

DATA IN

PM1 = 1 AND PM0 = 1 TO KEEP

THE PART IN THIS MODE

THE PART POWERS UP

FROM STANDBY ON SCLK

FALLING EDGE AS PM1 = 1

AND PM0 = 1

THE PART ENTERS

STANDBY AT THE END OF

CONVERSION AS

PM1 = 1 AND PM0 = 1

Figure 15. Autostandby Operation

Autostandby (PM1 = 1, PM0 = 1)

In this mode, the AD7888 automatically enters a standby (or

sleep) mode at the end of every conversion. In this standby

mode, all on-chip circuitry, apart from the on-chip reference, is

powered down. This mode is similar to the autoshutdown but

in this case, the power-up time is much shorter as the on-chip

reference remains powered up at all times.

Figure 15 shows the general diagram of the operation of the

AD7888 in this mode. On the first falling SCLK edge after CS

goes low, the AD7888 comes out of standby. The AD7888

wake-up time is very short in this mode so it is possible to wake

up the part and carry out a valid conversion in the same read/

write operation. The input signal is sampled on the second

rising edge of SCLK following the CS falling edge. At the end

of conversion (last rising edge of SCLK) the part automatically

enters its standby mode.

REV. C

AD7888

–13–

SERIAL INTERFACE

Figure 16 shows the detailed timing diagram for serial interfac-

ing to the AD7888. The serial clock provides the conversion

clock and also controls the transfer of information to and from

the AD7888 during conversion.

CS initiates the data transfer and conversion process. For the

autoshutdown mode, the first falling edge of SCLK after the

falling edge of CS wakes up the part. In all cases, it gates the

serial clock to the AD7888 and puts the on-chip track/hold into

track mode. The input signal is sampled on the second rising

edge of the SCLK input after the falling edge of CS. Thus, the

first one and one-half clock cycles after the falling edge of CS is

when the acquisition of the input signal takes place. This time is

denoted as the acquisition time (t

ACQ

). In autoshutdown mode,

the acquisition time must allow for the wake-up time of 5 µs. The

on-chip track/hold goes from track mode to hold mode on the

second rising edge of SCLK and a conversion is also initiated on

this edge. The conversion process takes a further fourteen and

one-half SCLK cycles to complete. The rising edge of CS will

put the bus back into three-state. If CS is left low a new conver-

sion will be initiated.

The input channel that is sampled is the one selected in the

previous write to the Control Register. Thus, the user must

write ahead of the channel for conversion. In other words, the

user must write the channel address for the next conversion

while the present conversion is in progress.

DONTC

REF

ZERO

ADD2 ADD1 ADD0 PM1 PM0

SCLK

156

DOUT

DIN

234

ACQ

CONVERT

DB11

DB0

DB10 DB9

4 LEADING ZEROS

THREE-

STATE

THREE-

STATE

Figure 16. Serial Interface Timing Diagram

Writing of information to the Control Register takes place on

the first eight rising edges of SCLK in a data transfer. The Con-

trol Register is always written to when a data transfer takes

place. The user must be careful to always set up the correct

information on the DIN line when reading data from the part.

Sixteen serial clock cycles are required to perform the conver-

sion process and to access data from the AD7888. In applica-

tions where the first serial clock edge, following CS going low, is

a falling edge, this edge clocks out the first leading zero. Thus,

the first rising clock edge on the SCLK clock has the first lead-

ing zero provided. In applications where the first serial clock

edge, following CS going low, is a rising edge, the first leading

zero may not be set up in time for the processor to read it cor-

rectly. However, subsequent bits are clocked out on the falling

edge of SCLK so they are provided to the processor on the

following rising edge. Thus, the second leading zero is clocked

out on the falling edge subsequent to the first rising edge. The

final bit in the data transfer is valid on the 16th rising edge,

having being clocked out on the previous falling edge.

NOTE: The mark space ratio for SCLK is specified for at least

40% high time (with corresponding 60% low time) or 40% low

time (with corresponding 60% high time). As the SCLK frequency

is reduced, the mark space ratio may vary provided the conver-

sion time never exceeds 50 µs—to avoid capacitive droop effects.

REV. C

AD7888

–14–

MICROPROCESSOR INTERFACING

The serial interface on the AD7888 allows the part to be directly

connected to a range of many different microprocessors. This

section explains how to interface the AD7888 with some of the

more common microcontroller and DSP serial interface protocols.

AD7888 to TMS320C5x

The serial interface on the TMS320C5x uses a continuous serial

clock and frame synchronization signals to synchronize the data

transfer operations with peripheral devices like the AD7888.

The CS input allows easy interfacing with an inverter between

the serial clock of the TMS320C5x and the AD7888 being the

only glue logic required. The serial port of the TMS320C5x is

set up to operate in burst mode with internal CLKX (TX serial

clock) and FSX (TX frame sync). The serial port control register

(SPC) must have the following setup: FO = 0, FSM = 1, MCM

= 1 and TXM = 1. The connection diagram is shown in Figure 17.

AD7888*

DOUT

DIN

SCLK

TMS320C5x*

*ADDITIONAL PINS OMITTED FOR CLARITY

CLKX

CLKR

FSX

FSR

Figure 17. Interfacing to the TMS320C5x

AD7888 to ADSP-21xx

The ADSP-21xx family of DSPs are interfaced to the AD7888

with an inverter between the serial clock of the ADSP-21xx

and the AD7888. This is the only glue logic required. The SPORT

control register should be set up as follows:

TFSW = RFSW = 1, Alternate Framing

INVRFS = INVTFS = 1, Active Low Frame Signal

DTYPE = 00, Right Justify Data

SLEN = 1111, 16-Bit Data Words

ISCLK = 1, Internal Serial Clock

TFSR = RFSR = 1, Frame Every Word

IRFS = 0

ITFS = 1

The connection diagram is shown in Figure 18. The ADSP-

21xx has the TFS and RFS of the SPORT tied together with

TFS set as an output and RFS set as in input. The DSP oper-

ated in Alternate Framing Mode and the SPORT Control Reg-

ister is set up as described. The frame synchronization signal

generated on the TFS is tied to CS and, as with all signal pro-

cessing applications, equidistant sampling is necessary. How-

ever, in this example the timer interrupt is used to control the

sampling rate of the ADC and, under certain conditions, equi-

distant sampling may not be achieved.

The Timer Registers, etc., are loaded with a value that will

provide an interrupt at the required sample interval. When an

interrupt is received, a value is transmitted with TFS/DT (ADC

control word). The TFS is used to control the RFS and hence

the reading of data. The frequency of the serial clock is set in

the SCLKDIV Register. When the instruction to transmit with

TFS is given, (i.e., AX0 = TX0), the state of the SCLK is checked.

The DSP will wait until the SCLK has gone high, low and high

before transmission will start. If the timer and SCLK values are

chosen such that the instruction to transmit occurs on or near

the rising edge of SCLK, the data may be transmitted or it may

wait until the next clock edge.

For example, the ADSP-2111 has a master clock frequency of

16 MHz. If the SCLKDIV Register is loaded with the value 3, a

SCLK of 2 MHz is obtained, and eight master clock periods will

elapse for every one SCLK period. If the timer registers are

loaded with the value 803, then 100.5 SCLKs will occur between

interrupts and subsequently between transmit instructions. The

situation will result in nonequidistant sampling as the transmit

instruction is occurring on a SCLK edge. If the number of SCLKs

between interrupts is not a figure of N.5, equidistant sampling

will be implemented by the DSP.

AD7888*

DOUT

DIN

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

SCLK

RFS

TFS

ADSP-21xx*

Figure 18. Interfacing to the ADSP-21xx

AD7888 to DSP56xxx

The connection diagram in Figure 19 shows how the AD7888

can be connected to the SSI (Synchronous Serial Interface) of

the DSP56xxx family of DSPs from Motorola. The SSI is oper-

ated in synchronous mode (SYN bit in CRB = 1) with internally

generated 1-bit clock period frame sync for both TX and RX

(bits FSL1 = 1 and FSL0 = 0 in CRB). Set the word length to

16 by setting bits WL1 = 1 and WL0 = 0 in CRA. An inverter is

also necessary between the SCLK from the DSP56xxx and the

SCLK pin of the AD7888 as shown in Figure 19.

DOUT

DIN

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

DSP56xxx*AD7888*

SCK

SRD

STD

SC2

Figure 19. Interfacing to the DSP56xxx

REV. C

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

AD7888ARUZ-REEL7

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Buy AD7888ARUZ-REEL7

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 2.7V-5.25V Micropwr 8-Ch 125kSPS 12-Bit

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AD7888ARUZ-REEL7

AD7888ARUZ-REEL7

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