AD7888ARUZ-REEL7 Datasheet AD7888ARUZ-REEL7, AD7888ARUZ, AD7888ARZ | P7-P9

AD7888

–6–

TERMINOLOGY

Integral Nonlinearity

This is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function. The end-

points of the transfer function are zero scale, a point 1/2 LSB

below the first code transition, and full scale, a point 1/2 LSB

above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the first code transition (00 . . . 000) to

(00 . . . 001) from the ideal, i.e., AGND + 0.5 LSB.

Offset Error Match

This is the difference in offset error between any two channels.

Gain Error

This is the deviation of the last code transition (111 . . . 110) to

(111 . . . 111) from the ideal (i.e., V

REF

– 1.5 LSB) after the

offset error has been adjusted out.

Gain Error Match

This is the difference in gain error between any two channels.

Track/Hold Acquisition Time

The track/hold amplifier returns into track mode at the end of

conversion. Track/Hold acquisition time is the time required for

the output of the track/hold amplifier to reach its final value,

within ± 1/2 LSB, after the end of conversion.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the

output of the A/D converter. The signal is the rms amplitude of

the fundamental. Noise is the sum of all nonfundamental sig-

nals up to half the sampling frequency (f

/2), excluding dc. The

ratio is dependent on the number of quantization levels in the

digitization process; the more levels, the smaller the quantiza-

tion noise. The theoretical signal to (noise + distortion) ratio for

an ideal N-bit converter with a sine wave input is given by:

Signal to (Noise + Distortion) = (6.02 N + 1.76) dB

Thus for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of

harmonics to the fundamental. For the AD7888, it is defined as:

THD dB

VVVVV

( ) log=

++++

where V

is the rms amplitude of the fundamental and V

, V

and V

are the rms amplitudes of the second through the

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to f

/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is deter-

mined by the largest harmonic in the spectrum, but for ADCs

where the harmonics are buried in the noise floor, it will be a

noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa ± nfb where

m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are

those for which neither m nor n is equal to zero. For example,

the second order terms include (fa + fb) and (fa – fb), while the

third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and

(fa – 2fb).

The AD7888 is tested using the CCIF standard where two

input frequencies near the top end of the input bandwidth are

used. In this case, the second order terms are usually distanced

in frequency from the original sine waves while the third order

terms are usually at a frequency close to the input frequencies.

As a result, the second and third order terms are specified sepa-

rately. The calculation of the intermodulation distortion is as

per the THD specification where it is the ratio of the rms sum of

the individual distortion products to the rms amplitude of the

sum of the fundamentals expressed in dBs.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of crosstalk

between channels. It is measured by applying a full-scale 25 kHz

sine wave signal to all nonselected input channels and determin-

ing how much that signal is attenuated in the selected channel.

The figure given is the worst case across all four or eight chan-

nels for the AD7888.

PSR (Power Supply Rejection)

Variations in power supply will affect the full-scale transition,

but not the converter’s linearity. Power supply rejection is the

maximum change in the full-scale transition point due to a

change in power-supply voltage from the nominal value.

REV. C

AD7888

–7–

CONTROL REGISTER

The Control Register on the AD7888 is an 8-bit, write-only register. Data is loaded from the DIN pin of the AD7888 on the rising

edge of SCLK. The data is transferred on the DIN line at the same time as the conversion result is read from the part. This requires

16 serial clocks for every data transfer. Only the information provided on the first 8 rising clock edges (after CS falling edge) is loaded

to the Control Register. MSB denotes the first bit in the data stream. The bit functions are outlined in Table I. The default contents

of the Control Register on power-up is all zeros.

Table I. Control Register Bit Function Description

MSB

CTNODOREZ2DDA1DDA0DDAFER1MP0MP

Bit Mnemonic Comment

7 DONTC Don’t Care. The value written to this bit of the Control Register is a don’t care, i.e., it doesn’t matter if the bit is

0 or 1.

6 ZERO A zero must be written to this bit to ensure correct operation of the AD7888.

5 ADD2 These three address bits are loaded at the end of the present conversion sequence and select which analog input

4 ADD1 channel is converted for the next conversion. The selected input channel is decoded as shown in Table II.

3 ADD0

2 REF Reference Bit. With a 0 in this bit, the on-chip reference is enabled. With a 1 in this bit, the on-chip reference

is disabled. To obtain best performance from the AD7888, the internal reference should be disabled when

using an externally applied reference source. (See On-Chip Reference section.)

1, 0 PM1, PM0 Power Management Bits. These two bits decode the mode of operation of the AD7888 as shown in Table III.

PERFORMANCE CURVES

Figure 2 shows a typical FFT plot for the AD7888 at 100 kHz

sample rate and 10 kHz input frequency.

FREQUENCY – kHz

–10

0 48.83

12.21 24.41 36.62

–30

–50

–70

–90

–110

4096 POINT FFT

SAMPLING

100kSPS

= 10kHz

SNR = 70dB

Figure 2. Dynamic Performance

Figure 3 shows a typical plot for the SNR vs. frequency for a

5 V supply and with a 5 V external reference.

71.0

0 42.14

SNR – dB

73.0

72.5

72.0

71.5

10.89 31.59

= 5V

5V EXT REFERENCE

21.14

INPUT FREQUENCY – kHz

Figure 3. SNR vs. Input Frequency

REV. C

AD7888

–8–

Figure 4 shows the typical power supply rejection ratio vs.

frequency for the part. The power supply rejection ratio is defined

as the ratio of the power in the ADC output at frequency f

to the power of a full-scale sine wave applied to the ADC of

frequency fs:

PSRR (dB) = 10 log (Pf/Pfs)

Pf = Power at frequency f in ADC output, Pfs = power at fre-

quency fs in ADC full scale input. Here a 100 mV peak-to-peak

sine wave is coupled onto the V

supply. Both the 2.7 V and

5.5 V supply performances are shown.

INPUT FREQUENCY – kHz

–93

2.65

64.15

PSRR – dB

12.85 33.65

= 5.5V/2.7V

100mV p-p SINE WAVE ON V

REF

= 2.488V EXT REFERENCE

23.15

–91

–89

–87

–85

–83

–81

–79

–77

–75

43.85

54.35

Figure 4. PSRR vs. Frequency

CIRCUIT INFORMATION

The AD7888 is a fast, low power, 12-bit, single supply, 8-channel

A/D converter. The part can be operated from 3 V (2.7 V to

3.6 V) supply or from 5 V (4.75 V to 5.25 V) supply. When

operated from either a 5 V supply or a 3 V supply, the AD7888

is capable of throughput rates of 125 kSPS when provided with

a 2 MHz clock.

The AD7888 provides the user with an 8-channel multiplexer,

on-chip track/hold, A/D converter, reference and serial interface

housed in a tiny 16-lead TSSOP package, which offers the user

considerable space saving advantages over alternative solutions.

The serial clock input accesses data from the part and also

provides the clock source for the successive-approximation

A/D converter. The analog input range is 0 to V

REF

(where

the externally-applied V

REF

can be between 1.2 V and V

The 8-channel multiplexer is controlled by the part’s Control

the internal reference and to determine the Modes of Operation.

CONVERTER OPERATION

The AD7888 is a successive-approximation analog-to-digital

converter based around a charge redistribution DAC. Figures 5

and 6 show simplified schematics of the ADC. Figure 5 shows

the ADC during its acquisition phase. SW2 is closed and SW1 is

in Position A, the comparator is held in a balanced condition

and the sampling capacitor acquires the signal on AIN.

CHARGE

REDISTRIBUTION

DAC

(REF IN/REF OUT)/2

SAMPLING

CAPACITOR

COMPARATOR

CONTROL

LOGIC

ACQUISITION

PHASE

SW1

SW2

AGND

AIN

Figure 5. ADC Acquisition Phase

When the ADC starts a conversion, (see Figure 6), SW2 will open

and SW1 will move to Position B causing the comparator to

become unbalanced. The control logic and the charge redistribu-

tion DAC are used to add and subtract fixed amounts of charge

from the sampling capacitor to bring the comparator back into a

balanced condition. When the comparator is rebalanced, the

conversion is complete. The control logic generates the ADC

output code. Figure 7 shows the ADC transfer function.

CONVERSION

PHASE

CHARGE

REDISTRIBUTION

DAC

(REF IN/REF OUT)/2

SAMPLING

CAPACITOR

COMPARATOR

CONTROL

LOGIC

SW1

SW2

AGND

VIN

Figure 6. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding of the AD7888 is straight binary. The

designed code transitions occur at successive integer LSB

values (i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = V

REF

4096. The ideal transfer characteristic for the AD7888 is

shown in Figure 7 below.

ADC CODE

ANALOG INPUT

111...000

011...111

0.5LSB

REF

– 1.5LSB

1LSB = V

REF

/4096

111...111

111...110

000...010

000...001

000...000

Figure 7. Transfer Characteristic

REV. C

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

AD7888ARUZ-REEL7

Mfr. #:

Buy AD7888ARUZ-REEL7

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 2.7V-5.25V Micropwr 8-Ch 125kSPS 12-Bit

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

AD7888ARUZ-REEL7

AD7888ARUZ-REEL7

Products related to this Datasheet