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PCF8575CTS/1,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
1999 Aug 05 13
Philips Semiconductors Product specification
Remote 16-bit I/O expander for I
2
C-bus
PCF8575C
8 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); note 1.
Note
1. Stress above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is
a stress ratings only and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
9 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC12 under
“Handling MOS Devices”
.
10 CHARACTERISTICS
V
DD
= 4.5 to 5.5 V; V
SS
=0V; T
amb
= −40 to +85 °C; unless otherwise specified.
SYMBOL PARAMETER MIN. MAX. UNIT
V
DD
supply voltage −0.5 +6.5 V
I
DD
supply current −±100 mA
I
SS
supply current −±100 mA
V
I
input voltage V
SS
− 0.5 V
DD
+ 0.5 V
I
I
DC input current −±20 mA
I
O
DC output current −±25 mA
P
tot
total power dissipation − 400 mW
P
O
power dissipation per output − 100 mW
T
stg
storage temperature −65 +150 °C
T
amb
ambient temperature −40 +85 °C
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
V
DD
supply voltage 4.5 − 5.5 V
I
DD
supply current operating mode; no
load; V
I
=V
DD
or V
SS
;
f
SCL
= 400 kHz
− 100 200 µA
I
DD(stb)
standby current standby mode; no load;
V
I
=V
DD
or V
SS
− 2.5 10 µA
V
POR
Power-on reset voltage note 1 − 1.2 1.8 V
V
IL1
LOW-level input voltage
pins A0, A1, A2, SDA and SCL
−0.8 − 0.3V
DD
V
V
IL2
LOW-level input voltage
pins P00 to P17
−0.8 − 0.6V
DD
V
V
IH1
HIGH-level input voltage
pins A0, A1, A2, SDA and SCL
0.7V
DD
− V
DD
+ 0.8 V
V
IH2
HIGH-level input voltage
pins P00 to P17
0.8V
DD
− V
DD
+ 0.8 V
1999 Aug 05 14
Philips Semiconductors Product specification
Remote 16-bit I/O expander for I
2
C-bus
PCF8575C
Notes
1. The Power-on reset circuit resets the I
2
C-bus logic with V
DD
<V
POR
and sets all I/Os to logic 1 (with current source
to V
DD
).
2. The value is not tested, but verified on sampling basis.
3. A single LOW-level output current (I
OL
) must not exceed 20 mA for an extended time. The sum of all I
OLs
at any point
in time must not exceed 100 mA.
I
L
leakage current at all pins V
I
=V
DD
or V
SS
−2 − +2 µA
I
IHL
current through protection diode V
I
>V
DD
or V
I
<V
SS
;
note 2
−−±2mA
Input SCL; input/output SDA
I
OL
LOW-level output current V
OL
= 0.4 V; note 3 3 −−mA
C
I
input capacitance V
I
=V
SS
; note 2 −−7pF
I/Os; P00 to P07 and P10 to P17
I
OL
LOW-level output current V
OL
= 1 V; note 3 10 25 − mA
I
OHt
transient pull-up current V
OH
=V
SS
; see Fig.5 −0.5 −1.0 − mA
C
I
input capacitance note 2 −−10 pF
C
O
output capacitance note 2 −−10 pF
Port timing; C
L
≤ 100 pF (see Figs 5 and 6)
t
pv
output data valid −−4µs
t
su
input data set-up time 0 −−µs
t
h
input data hold time 4 −−µs
Interrupt INT (see Fig.13)
I
OL
LOW-level output current V
OL
= 0.4 V 1.6 −−mA
TIMING;C
L
≤100 PF (see Figs 5 and 6)
t
iv
input data valid time −−4µs
t
ir
reset delay time −−4µs
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1999 Aug 05 15
Philips Semiconductors Product specification
Remote 16-bit I/O expander for I
2
C-bus
PCF8575C
11 I
2
C-BUS TIMING CHARACTERISTICS
See Fig.13 and note 1.
Notes
1. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to V
IL
and V
IH
with an input voltage swing of V
SS
to V
DD
.
2. The device inputs SDA and SCL are filtered and will reject spikes on the bus lines of widths less than t
SW(max)
.
3. The rise and fall times specified here refer to the driver device (PCF8575C) and are part of the general fast I
2
C-bus
specification when PCF8575C asserts an acknowledge on SDA, the minimum fall time is 20 ns + 0.1C
b
.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
f
SCL
SCL clock frequency − 400 kHz
t
SW
tolerable spike width on bus note 2 − 50 ns
t
BUF
BUS free time between a STOP
and START condition
1.3 −µs
t
SU;STA
START condition set-up time 0.6 −µs
t
HD;STA
START condition hold time 0.6 −µs
t
LOW
SCL LOW time 1.3 −µs
t
HIGH
SCL HIGH time 0.6 −µs
t
r
SCL and SDA rise time note 3 20 + 0.1C
b
300 ns
t
f
SCL and SDA fall time note 3 20 + 0.1C
b
300 ns
t
SU;DAT
data set-up time 100 − ns
t
HD;DAT
data hold time 0 − ns
t
SU;STO
STOP condition set-up time 0.6 −µs
C
b
capacitive load represented by
each bus line
− 400 pF
handbook, full pagewidth
PROTOCOL
SCL
SDA
MGL546
BIT 0
LSB
(R/W)
t
SU;STA
t
SU;DAT
t
SU;STO
t
HD;STA
t
HD;DAT
t
BUF
t
r
t
f
t
LOW
t
HIGH
1/f
SCL
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 6
(A6)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
Fig.13 I
2
C-bus timing diagram.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

PCF8575CTS/1,112

Mfr. #:
Buy PCF8575CTS/1,112
Manufacturer:
NXP Semiconductors
Description:
Interface - I/O Expanders REMOTE I/O EXPANDER
Lifecycle:
New from this manufacturer.
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