U430/431
Vishay Siliconix
Document Number: 70249
S-04031—Rev. E, 04-Jun-01
www.vishay.com
8-1
Matched N-Channel Pairs
PRODUCT SUMMARY
Part Number V
GS(off)
(V) V
(BR)GSS
Min (V) g
fs
Min (mS) I
G
Typ (pA) jV
GS1
– V
GS2
j Typ (mV)
U430 –1 to –4 –25 10 –15 25
U431 –2 to –6 –25 10 –15 25
FEATURES BENEFITS APPLICATIONS
D Two-Chip Design
D High Slew Rate
D Low Offset/Drift Voltage
D Low Gate Leakage: 15 pA
D Low Noise
D High CMRR: 75 dB
D Tight Differential Match vs. Current
D Improved Op Amp Speed, Settling Time Accuracy
D Minimum Input Error/Trimming Requirement
D Insignificant Signal Loss/Error Voltage
D High System Sensitivity
D Minimum Error with Large Input Signals
D Wideband Differential Amps
D High-Speed, Temp-Compensated,
Single-Ended Input Amps
D High-Speed Comparators
D Impedance Converters
DESCRIPTION
The U430/431 are matched JFET pairs assembled in a TO-78
package. These devices offer good power gain even at
frequencies beyond 250 MHz.
The TO-78 package is available with full military processing
(see Military Information).
For similar products, see the low-noise U/SST401 series, the
high-gain 2N5911/5912, and the low-leakage U421/423 data
sheets.
1
TO-78
Top View
D
1
S
1
2
3
7
6
5
G
1
S
2
G
2
D
2
4
Case
ABSOLUTE MAXIMUM RATINGS
Gate-Drain, Gate-Source Voltage –25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate Current 10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead Temperature (
1
/
16
” from case for 10 sec.) 300 _C. . . . . . . . . . . . . . . . . .
Storage Temperature –65 to 200_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Junction Temperature –55 to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation : Per Side
a
300 mW. . . . . . . . . . . . . . . . . . . . . . . .
Total
b
500 mW. . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes
a. Derate 2.4 mW/_C above 25_C
b. Derate 4 mW/_C above 25_C
