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85211AMI-01LF

P1-P3P4-P6P7-P9P10-P12P13-P14
Low Skew, 1-to-2
Differential-to-HSTL Fanout Buffer
85211I-01
DATASHEET
85211I-01 REVISION B 6/12/15 1 ©2015 Integrated Device Technology, Inc.
BLOCK DIAGRAM PIN ASSIGNMENT
GENERAL DESCRIPTION
The 85211I-01 is a low skew, high performance 1-to-2
Differential-to-HSTL Fanout Buffer The CLK, nCLK pair can
accept most standarddifferential input levels.The 85211I-01 is
characterized to operate from a 3.3V power supply. Guaranteed
output and part-to-part skew characteristics make the 85211I-01
ideal for those clock distribution applications demanding well
defi ned performance and repeatability. For optimal performance,
terminate all outputs.
FEATURES
• Two differential HSTL compatible outputs
• One differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, HSTL, SSTL, HCSL
• Maximum output frequency: 700MHz
• Translates any single-ended input signal to HSTL
levels with resistor bias on nCLK input
• Output skew: 30ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 1ns (maximum)
• Output crossover Voltage: 0.68V to 0.9V
• Output duty cycle: 49% - 51% up to 266.6MHz
• V
OH
= 1.4V (maximum)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free RoHS-compliant package
•
For functional replacement use 8523
85211I-01
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
Q0
nQ0
Q1
nQ1
1
2
3
4
VDD
CLK
nCLK
GND
8
7
6
5
Q0
nQ0
Q1
nQ1
CLK
nCLK
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
85211I-01 DATA SHEET
2 REVISION B 6/12/15
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs Outputs
Input to Output Mode Polarity
CLK nCLK Q0, Q1 nQ0, nQ1
0 0 LOW HIGH Differential to Differential Non Inverting
1 1 HIGH LOW Differential to Differential Non Inverting
0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inverting
1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inverting
Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inverting
Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inverting
NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”.
Number Name Type Description
1, 2 Q0, nQ0 Output Differential output pair. HSTL interface levels.
3, 4 Q1, nQ1 Output Differential output pair. HSTL interface levels.
5 GND Power Power supply ground.
6 nCLK Input
Pullup/
Pulldown
Inverting differential clock input. V
DD
/2 default when left fl oating.
7 CLK Input Pulldown Non-inverting differential clock input.
8V
DD
Power Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51
kΩ
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
REVISION B 6/12/15
85211I-01 DATA SHEET
3 LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, V
DD
= 3.3V ± 5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Power Supply Voltage 3.135 3.3 3.465 V
I
DD
Power Supply Current 22 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current
nCLK V
DD
= V
IN
= 3.465V 150 µA
CLK V
DD
= V
IN
= 3.465V 150 µA
I
IL
Input Low Current
nCLK V
DD
= 3.465V, V
IN
= 0V -150 µA
CLK V
DD
= 3.465V, V
IN
= 0V -5 µA
V
PP
Peak-to-Peak Input Voltage 0.15 1.3 V
V
CMR
Common Mode Input Voltage;
NOTE 1, 2
0.5 V
DD
- 0.85 V
NOTE 1: For single ended applications the maximum input voltage for CLK and nCLK is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defi ned as V
IH
.
TABLE 4C. HSTL DC CHARACTERISTICS, V
DD
= 3.3V ± 5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OH
Output High Voltage; NOTE 1 1.0 1.4 V
V
OL
Output Low Voltage; NOTE 1 0 0.4 V
V
OX
Output Crossover Voltage 0.68 0.9 V
V
SWING
Peak-to-Peak Output Voltage Swing 0.6 1.0 1.4 V
NOTE 1: All outputs must be terminated with 50Ω to ground.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
DD
= 3.3V ± 5%, TA = -40°C TO 85°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
DD
-0.5V to V
DD
+ 0.5 V
Outputs, V
DD
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance, θ
JA
112.7°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
P1-P3P4-P6P7-P9P10-P12P13-P14

85211AMI-01LF

Mfr. #:
Buy 85211AMI-01LF
Manufacturer:
IDT
Description:
Clock Buffer Low Skew 1-to-2 Diff .-to-LVHSTL Fanout B
Lifecycle:
New from this manufacturer.
Delivery:
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