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85211AMI-01LF

P1-P3P4-P6P7-P9P10-P12P13-P14
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
85211I-01 DATA SHEET
4 REVISION B 6/12/15
TABLE 5. AC CHARACTERISTICS, V
DD
= 3.3V ± 5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 700 MHz
t
PD
Propagation Delay; NOTE 1 ƒ ≤ 600MHz 0.7 1.0 ns
tsk(o) Output Skew; NOTE 2, 4 30 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 250 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 200 500 ps
odc Output Duty Cycle
48 52 %
ƒ ≤ 266.6MHz 49 51 %
All parameters measured at 600MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defi ned as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.
REVISION B 6/12/15
85211I-01 DATA SHEET
5 LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART-TO-PART SKEWOUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME PROPAGATION DELAY
PARAMETER MEASUREMENT INFORMATION
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
85211I-01 DATA SHEET
6 REVISION B 6/12/15
SCHEMATIC EXAMPLE
Figure 2 shows a schematic example of 85211I-01. In this
example, the input is driven by an ICS HiPerClockS HSTL driver.
The decoupling capacitors should be physically located near
FIGURE 2. 85211I-01 HSTL BUFFER SCHEMATIC EXAMPLE
the power pin. For 85211I-01, the unused outputs
need to be terminated.
APPLICATION INFORMATION
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
of R1 and R2 might need to be adjusted to position the V_REF
in the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
C1
0.1u
R4
50
U1
ICS85211-01
1
2
3
4
8
7
6
5
Q0
nQ0
Q1
nQ1
VDD
CLK
nCLK
GND
Zo = 50 Ohm
R3
50
R1
50
Zo = 50 Ohm
1.8V
Zo = 50 Ohm
R5
50
Zo = 50 Ohm
LVHSTL
LVHSTL Driv er
VDD=3.3V
HiPerClockS
R2
50
ICS
Unused
Output
Need To
Be
Terminated
R6
50
LVHSTL Input
+
-
P1-P3P4-P6P7-P9P10-P12P13-P14

85211AMI-01LF

Mfr. #:
Buy 85211AMI-01LF
Manufacturer:
IDT
Description:
Clock Buffer Low Skew 1-to-2 Diff .-to-LVHSTL Fanout B
Lifecycle:
New from this manufacturer.
Delivery:
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