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MAX9244EUM/V+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
16 ______________________________________________________________________________________
DC-coupled link (2.4V - 1.425V = 0.975V and 1.075V -
0V = 1.075V). Common-mode voltage differences may
be due to ground potential variation or common-mode
noise. If there is more than ±1V of difference, the receiver
is not guaranteed to read the input signal correctly and
may cause bit errors. AC-coupling filters low-frequency
ground shifts and common-mode noise and passes
high-frequency data. A common-mode voltage differ-
ence up to the voltage rating of the coupling capacitor
(minus half the differential swing) is tolerated. DC-bal-
anced coding of the data is required to maintain the
differential signal amplitude and limit jitter on an
AC-coupled link. A capacitor in series with each output
of the LVDS driver is sufficient for AC-coupling. However,
two capacitors—one at the serializer output and one at
the deserializer input—provide protection in case either
end of the cable is shorted to a high voltage.
Applications Information
Selection of AC-Coupling Capacitors
Voltage droop and the DSV of transmitted symbols
cause signal transitions to start from different voltage
levels. Because the transition time is finite, starting the
signal transition from different voltage levels causes
timing jitter. The time constant for an AC-coupled link
needs to be chosen to reduce droop and jitter to an
acceptable level.
The RC network for an AC-coupled link consists of the
LVDS receiver termination resistor (R
T
), the LVDS driver
output resistor (R
O
), and the series AC-coupling capac-
itors (C). The RC time constant for two equal-value
series capacitors is (C x (R
T
+ R
O
)) / 2 (Figure 19). The
RC time constant for four equal-value series capacitors
is (C x (R
T
+ R
O
)) / 4 (Figure 20).
RPLLS (65,600 x RCIP)
LOW
LOW
RxCLKOUT
INTERNAL
PLL1 LOCK
INTERNAL
SSPLL LOCK
RxOUT_
LOW
LOW
Figure 16. Output Waveforms when PLL1 Loses Lock and Locks Again
RPLLS2 (32,800 x RCIP)
LOW
INTERNAL
SSPLL LOCK
RxCLKOUT
RxOUT_
TIMING SHOWN FOR STABLE CLOCK AND DATA INPUTS
Figure 17. Output Waveforms if Spread-Spectrum PLL Loses Lock and Locks Again
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
______________________________________________________________________________________ 17
R
T
is required to match the transmission line impedance
(usually 100Ω) and R
O
is determined by the LVDS dri-
ver design (the minimum differential output resistance of
78Ω for the MAX9209/MAX9213 serializers is used in
the following example). This condition leaves the capac-
itor selection to change the system time constant.
In the following example, the capacitor value for a 2%
droop is calculated. Jitter due to this droop is then cal-
culated assuming a 1ns transition time:
C = -(2 x t
B
x DSV) / (ln (1 - D) x (R
T
+ R
O
)) (Eq 1)
where:
C = AC-coupling capacitor (F)
t
B
= bit time (s)
DSV = digital sum variation (integer)
ln = natural log
D = droop (% of signal amplitude)
R
T
= termination resistor (Ω)
R
O
= output resistance (Ω)
Equation 1 is for two series capacitors (Figure 19). The bit
time (t
B
) is the period of the parallel clock divided by 9.
The DSV is 10. See equation 3 for four series capacitors
(Figure 20).
The capacitor for 2% maximum droop at 16MHz parallel
rate clock is:
C = -(2 x t
B
x DSV) / (ln (1 - D) x (R
T
+ R
O
))
C = -(2 x 6.95ns x 10) / (ln (1 - 0.02) x (100Ω + 78Ω))
C = 0.038µF
Jitter due to droop is proportional to the droop and
transition time:
t
J
= t
T
x D (Eq 2)
where:
t
J
= jitter (s)
t
T
= transition time (s) (0 to 100%)
D = droop (% of signal amplitude)
Jitter due to 2% droop and assumed 1ns transition time is:
t
J
= 1ns x 0.02
t
J
= 20ps
The transition time in a real system depends on the fre-
quency response of the cable driven by the serializer.
Figure 18. DC-Coupled Link, Non-DC-Balanced Mode
7:1
1:7 FIFO
7
7
100Ω
7:1
1:7 FIFO
7
7
100Ω
7:1
1:7 FIFO
7
7
100Ω
PLL
PLL1 +
SSPLL
100Ω
MAX9209/MAX9213 MAX9242/MAX9244/MAX9246/MAX9254
TxOUT
TxCLK OUT
RxIN__
RxCLK IN
21:3 SERIALIZER 3:21 DESERIALIZER
PWRDWN
RxCLK OUT
RxOUT_
PWRDWN
TxCLK IN
TxIN
TRANSMISSION LINE
R
O
R
T
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
18 ______________________________________________________________________________________
The capacitor value decreases for a higher frequency
parallel clock and for higher levels of droop and jitter.
Use high-frequency, surface-mount ceramic capacitors.
Equation 1 altered for four series capacitors (Figure 20) is:
C = -(4 x t
B
x DSV) / (ln (1 - D) x (R
T
+ R
O
)) (Eq 3)
Fail-Safe
The MAX9242/MAX9244/MAX9246/MAX9254 have fail-
safe LVDS inputs in non-DC-balanced mode (Figure 1).
Fail-safe drives the outputs low when the corresponding
LVDS input is open, undriven and shorted, or undriven
and parallel terminated. The fail-safe on the LVDS clock
input drives all outputs low when power is stable. Fail-
safe does not operate in DC-balanced mode.
Input Bias and Frequency Detection
In DC-balanced mode, the inverting and noninverting
LVDS inputs are internally connected to +1.2V through
42kΩ (min) to provide biasing for AC-coupling (Figure 1).
To prevent switching due to noise when the clock input
is not driven, bias the clock inputs (RxCLKIN+,
RxCLKIN-) to differential +15mV by connecting a 10kΩ
±1% pullup resistor between the noninverting input and
LVDSV
CC
, and a 10kΩ ±1% pulldown resistor between
the inverting input and ground. These bias resistors,
along with the 100Ω ±1% tolerant termination resistor,
provide +15mV of differential input. The +15mV bias
causes some small degradation of RSKM proportional to
the slew rate of the clock input. For example, if the clock
transitions 250mV in 500ps, the slew rate of 0.5mV/ps
reduces RSKM by 30ps.
Unused LVDS Data Inputs
In non-DC-balanced mode, leave unused LVDS data
inputs open. In non-DC-balanced mode, the input fail-
safe circuit drives the corresponding outputs low, and no
pullup or pulldown resistors are needed. In DC-balanced
mode, at each unused LVDS data input, pull the inverting
input up to LVDSV
CC
using a 10kΩ resistor, and pull the
noninverting input down to ground using a 10kΩ resistor.
Do not connect a termination resistor. The pullup and
pulldown resistors drive the corresponding outputs low
and prevent switching due to noise.
(7 + 2):1
7
7
100Ω
(7 + 2):1
7
7
100Ω
(7 + 2):1
1:(9 - 2)
+ FIFO
1:(9 - 2)
+ FIFO
1:(9 - 2)
+ FIFO
7
7
100Ω
PLL
100Ω
MAX9209/MAX9213 MAX9242/MAX9244/MAX9246/MAX9254
TxOUT
TxCLK OUT
RxIN__
RxCLK IN
21:3 SERIALIZER 3:21 DESERIALIZER
PWRDWN
RxCLK OUT
RxOUT_
PWRDWN
TxCLK IN
TxIN
HIGH-FREQUENCY, CERAMIC
SURFACE-MOUNT CAPACITORS
CAN ALSO BE PLACED AT THE
SERIALIZER INSTEAD OF THE DESERIALIZER.
PLL1 +
SSPLL
R
O
R
T
Figure 19. Two Capacitors per Link, AC-Coupled, DC-Balanced Mode
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

MAX9244EUM/V+T

Mfr. #:
Buy MAX9244EUM/V+T
Manufacturer:
Maxim Integrated
Description:
Serializers & Deserializers - Serdes 21-Bit DC-Balanced LVDS Deserialize
Lifecycle:
New from this manufacturer.
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