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MAX9244EUM/V+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
4 _______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS
(V
CC
= LVDSV
CC
= PLLV
CC
= +3.0V to +3.6V, V
CCO
= +3.0V to +3.6V, C
L
= 8pF, PWRDWN = high; SSG = high, open, or low;
DCB = high or low, differential input voltage |V
ID
| = 0.1V to 1.2V, input common-mode voltage V
CM
= |V
ID
/ 2| to 2.4V - |V
ID
/ 2|, unless
otherwise noted. Typical values are at V
CC
= V
CCO
= LVDSV
CC
= PLLV
CC
= +3.3V, |V
ID
| = 0.2V, V
CM
= +1.25V, T
A
= +25°C.) (Notes 6, 7, 8)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
RxOUT_ 2.9 4.7 6.5
Output Rise Time CLHT
0.1 x V
C C O
to 0.9 x V
C C O
,
Fi g ur e 3
RxCLKOUT 2.0 3.3 4.1
ns
RxOUT_ 2.1 3.0 4.2
Output Fall Time CHLT
0.9 x V
C C O
to 0.1 x V
C C O
,
Fi g ur e 3
RxCLKOUT 1.10 1.94 2.70
ns
Output Rise Time (MAX9254) CLHT
0.1 x V
C C O
to 0.9 x V
C C O
,
Fi g ur e 3
RxOUT_ 1.4 2.2 3.3 ns
Output Fall Time (MAX9254) CHLT
0.9 x V
C C O
to 0.1 x V
C C O
,
Fi g ur e 3
RxCLKOUT 1.1 1.8 2.8 ns
16MHz 2560 3142
DC-balanced mode,
Figure 4
34MHz 900 1386
20MHz 2500 3164
RxIN__ Skew Margin (Note 9) RSKM
Non-DC-balanced mode,
Figure 4
40MHz 960 1371
ps
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= LVDSV
CC
= PLLV
CC
= +3.0V to +3.6V, V
CCO
= +3.0V to +5.5V, PWRDWN = high; SSG = high, open, or low; DCB = high or
low, differential input voltage |V
ID
| = 0.05V to 1.2V, input common-mode voltage V
CM
= |V
ID
/ 2| to 2.4V - |V
ID
/ 2|, unless otherwise
noted. Typical values are at V
CC
= V
CCO
= LVDSV
CC
= PLLV
CC
= +3.3V, |V
ID
| = 0.2V, V
CM
= +1.25V, T
A
= +25°C.) (Notes 1, 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
High-Impedance Output Current I
OZ
PWRDWN = low, V
OUT
= -0.3V to (V
CCO
+ 0.3V) -30 +30 µA
RxCLKOUT (Note 4) -10 -40
V
CCO
= 3.0V to 3.6V,
V
OUT
= 0V
RxOUT_ -5 -20
RxCLKOUT (Note 4) -28 -75
Output Short-Circuit Current
(Note 5)
I
OS
V
CCO
= 4.5V to 5.5V,
V
OUT
= 0V
RxOUT_ -13 -37
mA
RxOUT_
V
CCO
= 3.0V to 3.6V,
V
OUT
= 0V
RxCLKOUT (Note 4)
-16 -51
RxOUT_
Output Short-Circuit Current
(MAX9254) (Note 5)
I
OS
V
CCO
= 4.5V to 5.5V,
V
OUT
= 0V
RxCLKOUT (Note 4)
-34 -93
mA
LVDS INPUTS (RxIN__, RxCLKIN_)
Differential Input High Threshold V
TH
(Note 6) 50 mV
Differential Input Low Threshold V
TL
(Note 6) -50 mV
Input Current I
IN+
, I
IN-
PWRDWN = high or low -25 +25 µA
Power-Off Input Current I
INO+
, I
INO-
V
CC
= V
CCO
= 0V or open -40 +40 µA
-40°C to +85°C 42 78
Input Resistor 1 R
IN1
PWRDWN = high or low,
V
CC
= V
CCO
= 0V or open,
Figure 1
-40°C to +105°C 42 85
kΩ
-40°C to +85°C 246 410
Input Resistor 2 R
IN2
PWRDWN = high or low,
V
CC
= V
CCO
= 0V or open,
Figure 1
-40°C to +105°C 246 440
kΩ
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
_______________________________________________________________________________________ 5
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground,
except V
TH
and V
TL
.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T
A
= +25°C.
Note 3: To provide a mid level, leave the input open, or, if driven, put driver in high impedance. High-impedance leakage current
must be less than ±10µA.
Note 4: RxCLKOUT limits are scaled based on RxOUT_ measurements, design, and characterization data.
Note 5: One output shorted at a time. Current out of the pin.
Note 6: V
TH
, V
TL
, and AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set
at ±6 sigma.
Note 7: C
L
includes probe and test jig capacitance.
Note 8: RCIP is the period of RxCLKIN_. RCOP is the period of RxCLKOUT.
Note 9: RSKM is measured with less than 150ps cycle-to-cycle jitter on RxCLKIN_.
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= LVDSV
CC
= PLLV
CC
= +3.0V to +3.6V, V
CCO
= +3.0V to +3.6V, C
L
= 8pF, PWRDWN = high; SSG = high, open, or low;
DCB = high or low, differential input voltage |V
ID
| = 0.1V to 1.2V, input common-mode voltage V
CM
= |V
ID
/ 2| to 2.4V - |V
ID
/ 2|, unless
otherwise noted. Typical values are at V
CC
= V
CCO
= LVDSV
CC
= PLLV
CC
= +3.3V, |V
ID
| = 0.2V, V
CM
= +1.25V, T
A
= +25°C.) (Notes 6, 7, 8)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
RxCLKOUT High Time RCOH Figures 5a, 5b
0.35 x
RCOP
ns
RxCLKOUT Low Time RCOL Figures 5a, 5b
0.35 x
RCOP
ns
RxOUT_ Setup to RxCLKOUT RSRC Figures 5a, 5b
0.3 x
RCOP
ns
RxOUT_ Hold from RxCLKOUT RHRC Figures 5a, 5b
0.45 x
RCOP
ns
RxCLKIN_ to RxCLKOUT Delay RCCD SSG = low, Figures 6a, 6b
4.5 +
(RCIP / 2)
6.5 +
(RCIP / 2)
8.2 +
(RCIP / 2)
ns
Deserializer Phase-Locked-
Loop Set
RPLLS Figure 7
65,600 x
RCIP
ns
Deserializer Power-Down Delay RPDD Figure 8 100 ns
Deserializer Phase-Locked-
Loop Set from SSG Change
RPLLS2 Figure 9
32,800 x
RCIP
ns
M axi m um outp ut
fr eq uency
f
RxCLKIN_
+ 3.6%
f
RxCLKIN_
+ 4.0%
f
RxCLKIN_
+ 4.4%
SSG = high,
Figure 10
Minimum output
frequency
f
RxCLKIN_
- 4.4%
f
RxCLKIN_
- 4.0%
f
RxCLKIN_
- 3.6%
M axi m um outp ut
fr eq uency
f
RxCLKIN_
+ 1.8%
f
RxCLKIN_
+ 2.0%
f
RxCLKIN_
+ 2.2%
SSG = open,
Figure 10
Minimum output
frequency
f
RxCLKIN_
- 2.2%
f
RxCLKIN_
- 2.0%
f
RxCLKIN_
- 1.8%
Spread-Spectrum Output
Frequency
f
RxCLKOUT
SSG = low f
RxCLKIN_
f
RxCLKIN_
MHz
Spread-Spectrum Modulation
Frequency
f
SSM
Figure 10
f
RxCLKIN_
/
1016
Hz
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
6 _______________________________________________________________________________________
Test Circuits/Timing Diagrams
V
CC
- 0.3V
V
CC
R
IN2
R
IN1
RxIN_ + OR
RxCLKIN+
RxIN_ - OR
RxCLKIN-
R
IN1
R
IN1
RxIN_ + OR
RxCLKIN+
RxIN_ - OR
RxCLKIN-
R
IN1
FAIL-SAFE
COMPARATOR
DC-BALANCED MODENON-DC-BALANCED MODE
1.2V
Figure 1. LVDS Input Circuits
RCOP
RxCLKOUT
ODD RxOUT
EVEN RxOUT
Figure 2. Worst-Case Test Pattern
90%90%
10%10%
CHLTCLHT
RxOUT_ OR
RxCLKOUT
RxOUT_ OR
RxCLKOUT
8pF
Figure 3. Output Load and Transition Times
IDEAL
MIN MAX
INTERNAL STROBE
IDEAL
RSKM RSKM
IDEAL SERIAL BIT TIME
1.3V
1.1V
Figure 4. LVDS Receiver Input Skew Margin
RxOUT_
RxCLK OUT
RCOP
RCOHRCOL
2.0V
0.8V
2.0V
0.8V
2.0V
2.0V
2.0V
0.8V 0.8V
RHRCRSRC
Figure 5a. Rising-Edge Output Setup/Hold and High/Low Times
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

MAX9244EUM/V+T

Mfr. #:
Buy MAX9244EUM/V+T
Manufacturer:
Maxim Integrated
Description:
Serializers & Deserializers - Serdes 21-Bit DC-Balanced LVDS Deserialize
Lifecycle:
New from this manufacturer.
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