Technical Note
4/13
BD8301MUV
www.rohm.com
2009.09 - Rev.C
○
c
2009 ROHM Co., Ltd. All rights reserved.
●Description of Blocks
1.VREF
This block generates ERROR AMP reference voltage.
The reference voltage is 0.8 V.
2.UVLO
Circuit for preventing low voltage malfunction
Prevents malfunction of the internal circuit at activation of the power supply voltage or at low power supply voltage.
Monitors VCC pin voltage to turn off all output FET and DC/DC converter output when VCC voltage is lower than 2.2 V,
and reset the timer latch of the internal SCP circuit and soft-start circuit.
3.SCP
Timer latch system short-circuit protection circuit
When the INV pin is the set 0.8 V or lower voltage, the internal SCP circuit starts counting.
The internal counter is in synch with OSC; the latch circuit activates after the counter counts about 16000 oscillations to
turn off DC/DC converter output (about 16 msec when RT = 47kΩ).
To reset the latch circuit, turn off the STB pin once. Then, turn it on again or turn on the power supply voltage again.
4.OSC
Oscillation circuit to change frequency by external resistance of the RT pin (20 pin).
When RT = 47 kΩ, operation frequency is set at 1 MHz.
5.ERROR AMP
Error amplifier for detecting output signals and output PWM control signals
The internal reference voltage is set at 0.8 V.
6.PWM COMP
Voltage-pulse width converter for controlling output voltage corresponding to input voltage
Comparing the internal SLOPE waveform with the ERROR AMP output voltage, PWM COMP controls the pulse width
and outputs to the driver.
Max Duty and Min Duty are set at the primary side and the secondary side of the inductor respectively, which are as
follows:
Primary side (Lx1) Max Duty : 100 %,
Min Duty : 0 %
Secondary side (Lx2) Max Duty : 100 %,
Min Duty : About 15 %
7.SOFT START
Circuit for preventing in-rush current at startup by bringing the output voltage of the DC/DC converter into a soft-start
Soft-start time is in synch with the internal OSC, and the output voltage of the DC/DC converter reaches the set voltage
after about 1000 oscillations (About 1 msec when RT = 47 kΩ).
8.PRE DRIVER
CMOS inverter circuit for driving the built-in Pch/Nch FET
Dead time is provided for preventing feedthrough during switching.
The dead time is set at about 15 nsec for each individual SWs.
9. STBY_IO
Voltage applied on STB pin (19 pin) to control ON/OFF of IC
Turned ON when a voltage of 1.5 V or higher is applied and turned OFF when the terminal is open or 0 V is applied.
Incorporates approximately 400 kΩ pull-down resistance.
10. Pch/Nch FET SW
Built-in SW for switching the coil current of the DC/DC converter. Pch FET is about 120 mΩ and Nch is 100 mΩ.
Since the current rating of this FET is 2 A, it should be used within 2 A in total including the DC current and ripple current
of the coil.
