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ISL94201IRZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
4
FN6719.0
July 3, 2008
OVER-TEMPERATURE PROTECTION SPECIFICATIONS
Internal Temperature Shutdown
Threshold
T
INTSD
125 °C
Internal Temperature Hysteresis T
HYS
Temperature drop needed to restore
operation after over-temperature
shutdown.
20 °C
Internal Over-temperature Turn On
Delay Time
t
ITD
128 ms
External Temperature Output Current I
XT
Current output capability at TEMP3V pin 1.2 mA
External Temperature Limit Threshold T
XTF
Voltage at V
TEMPI
; Relative to falling
edge
-20 0 +20 mV
External Temperature Limit Hysteresis T
XTH
Voltage at V
TEMPI
. 60 110 160 mV
External Temperature Monitor Delay t
XTD
Delay between activating the external
sensor and the internal over-temperature
detection.
1ms
External Temperature Autoscan
On-Time
t
XTAON
TEMP3V is ON (3.3V) 5 ms
External Temperature Autoscan
Off-Time
t
XTAOFF
TEMP3V output is off. 635 ms
ANALOG OUTPUT SPECIFICATIONS
Cell Monitor Analog Output Voltage
Accuracy
V
AOC
[V
CELLN
- (V
CELLN-1
)]/2 - AO -15 4 30 mV
Cell Monitor Analog Output External
Temperature Accuracy
V
AOXT
External temperature monitoring accuracy.
Voltage error at AO when monitoring
TEMPI voltage (measured with
TEMPI = 1V)
-10 10 mV
Internal Temperature Monitor Output
Voltage Slope
V
INTMON
Internal temperature monitor voltage
change
-3.5 mV/°C
Internal Temperature Monitor Output T
INT25
Output at +25°C 1.31 V
AO Output Stabilization Time t
VSC
From SCL falling edge at data bit 0 of
command to AO output stable within 0.5%
of final value. AO voltage steps from 0V to
2V. (C
AO
= 10pF) (Note 7)
0.1 ms
WAKE UP/SLEEP SPECIFICATIONS
Device WKUP Pin Voltage Threshold
(WKUP Pin Active High - Rising Edge)
V
WKUP1
WKUP pin rising edge (WKPOL = 1)
Device wakes up and sets WKUP flag
HIGH.
3.5 5.0 6.5 V
Device Wkup Pin Hysteresis
(WKUP Pin Active High)
V
WKUP1H
WKUP pin falling edge hysteresis
(WKPOL = 1) sets WKUP flag LOW (does
not automatically enter sleep mode)
100 mV
Input Resistance On WKUP R
WKUP
Resistance from WKUP pin to VSS
(WKPOL = 1)
130 230 330 k
Device WKUP Pin Active Voltage
Threshold (WKUP Pin Active Low -
Falling Edge)
V
WKUP2
WKUP pin falling edge (WKPOL = 0)
Device wakes up and sets WKUP flag
HIGH.
V
CELL1
-2.6 V
CELL1
-2.0 V
CELL1
-1.2 V
Operating Specifications Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested (Continued)
PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT
V
TEMP3V
13
------------------------------
ISL94201
5
FN6719.0
July 3, 2008
Device Wkup Pin Hysteresis
(WKUP Pin Active Low)
V
WKUP2H
WKUP pin rising edge hysteresis
(WKPOL = 0) sets WKUP flag LOW (does
not automatically enter sleep mode).
200 mV
Device Wake-up Delay t
WKUP
Delay after voltage on WKUP pin crosses
the threshold (rising or falling) before
activating the WKUP bit.
20 40 60 ms
SERIAL INTERFACE CHARACTERISTICS
SCL Clock Frequency f
SCL
100 kHz
Pulse Width Suppression Time at
SDA and SCL Inputs
t
IN
Any pulse narrower than the max spec is
suppressed.
50 ns
SCL Falling Edge to SDA Output Data
Valid
t
AA
From SCL falling crossing V
IH
(min), until
SDA exits the V
IL
(max) to V
IH
(min)
window.
3.5 µs
Time the Bus Must Be Free Before
Start of New Transmission
t
BUF
SDA crossing V
IH
(min) during a STOP
condition to SDA crossing V
IH
(min) during
the following START condition.
4.7 µs
Clock Low Time t
LOW
Measured at the V
IL
(max) crossing. 4.7 µs
Clock High Time t
HIGH
Measured at the V
IH
(min) crossing. 4.0 µs
Start Condition Setup Time t
SU:STA
SCL rising edge to SDA falling edge. Both
crossing the V
IH
(min) level.
4.7 µs
Start Condition Hold Time t
HD:STA
From SDA falling edge crossing V
IL
(max)
to SCL falling edge crossing V
IH
(min).
4.0 µs
Input Data Setup Time t
SU:DAT
From SDA exiting the V
IL
(max) to V
IH
(min)
window to SCL rising edge crossing
V
IL
(min).
250 ns
Input Data Hold Time t
HD:DAT
From SCL falling edge crossing V
IH
(min) to
SDA entering the V
IL
(max) to V
IH
(min)
window.
300 µs
Stop Condition Setup Time t
SU:STO
From SCL rising edge crossing V
IH
(min) to
SDA rising edge crossing V
IL
(max).
4.0 µs
Stop Condition Hold Time t
HD:STO
From SDA rising edge to SCL falling edge.
Both crossing V
IH
(min).
4.0 µs
Data Output Hold Time t
DH
From SCL falling edge crossing V
IL
(max)
until SDA enters the V
IL
(max) to V
IH
(min)
window. (Note 4)
0ns
SDA and SCL Rise Time t
R
From V
IL
(max) to V
IH
(min). 1000 ns
SDA and SCL Fall Time t
F
From V
IH
(min) to V
IL
(max). 300 ns
Capacitive Loading Of SDA Or SCL
(Note 5)
Cb Total on-chip and off-chip 400 pF
SDA and SCL Bus Pull-up Resistor-
Off-Chip (Note 5)
R
OUT
Maximum is determined by t
R
and t
F
.
For C
B
= 400pF, max is about 2k~ 2.5k
For C
B
= 40pF, max is about 15k to 20k
1k
Input Leakage Current (SCL, SDA) I
LI
-10 10 µA
Input Buffer Low Voltage (SCL, SDA) V
IL
Voltage relative to V
SS
of the device. -0.3 V
RGO
x 0.3 V
Operating Specifications Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested (Continued)
PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT
ISL94201
6
FN6719.0
July 3, 2008
ISL94201
Wake up timing (WKPOL = 0)
Wake up timing (WKPOL = 1)
Change in Voltage Source
Input Buffer High Voltage (SCL, SDA) V
IH
Voltage relative to V
SS
of the device. V
RGO
x 0.7 V
RGO
+0.1 V
Output Buffer Low Voltage (SDA) V
OL
I
OL
= 1mA 0.4 V
SDA and SCL Input Buffer Hysteresis
(Note 5)
I
2
CHYST Sleep bit = 0 0.05 * V
RGO
V
NOTES:
3. Power-up of the device requires all V
CELL1
, V
CELL2
, V
CELL3
, and VCC to be above the limits specified.
4. The device provides an internal hold time of at least 300ns for the SDA signal to bridge the unidentified region of the falling edge of SCL.
5. Limits should be considered typical and are not production tested.
6. Typical 5 ±2, based on characterization data.
7. Maximum output capacitance = 15pF.
Operating Specifications Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested (Continued)
PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT
V
WKUP2
V
WKUP2H
t
WKUP
t
WKUP
<t
WKUP
<t
WKUP
WKUP PIN
WKUP BIT
V
WKUP1
V
WKUP1H
t
WKUP
t
WKUP
<t
WKUP
<t
WKUP
WKUP PIN
WKUP BIT
AO
t
VSC
t
VSC
BIT
0
SDA
SCL
BIT
0
DATA
BIT
1
BIT
2
BIT
3
BIT
1
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

ISL94201IRZ

Mfr. #:
Buy ISL94201IRZ
Manufacturer:
Renesas / Intersil
Description:
Battery Management MULTI-CELL LI-ION BATRY PACK ANALOG
Lifecycle:
New from this manufacturer.
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