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LTM8025IV#PBF

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LTM8025
13
8025fc
For more information www.linear.com/LTM8025
applicaTions inForMaTion
Figure 1. To Soft-Start the LTM8025, Add a Resistor and
Capacitor to the RUN/SS Pin
whether the RUN/SS is used. As shown in the Typical
Performance Characteristics section, the minimum input
voltage to run a 3.3V output at light load is only about 3.6V,
but, if the RUN/SS is pulled up to V
IN
, it takes 5.5V
IN
to
start. If the LTM8025 is enabled with the RUN/SS pin, the
minimum voltage to start at light loads is lower, about 4.3V.
Similar curves detailing this behavior of the LTM8025 for
other outputs are also included in the Typical Performance
Characteristics section.
Soft-Start
The RUN/SS pin can be used to soft-start the LTM8025,
reducing the maximum input current during start-up.
The RUN/SS pin is driven through an external RC filter to
create a voltage ramp at this pin, as shown in Figure 1.
By choosing an appropriate RC time constant, the peak
start-up current can be reduced to the current that is re
-
quired to regulate the output, with no overshoot. Choose
the value of the resistor so that it can supply at least 20μA
when the RUN/SS pin reaches 2.5V.
Frequency Foldback
8025 F01
RUN/SS
RUN
GND
15k
0.22µF
The LTM8025 is equipped with frequency foldback which
acts to reduce the thermal and energy stress on the internal
power elements during a short circuit or output overload
condition. If the LTM8025 detects that the output has fallen
out of regulation, the switching frequency is reduced as a
function of how far the output is below the target voltage.
This in turn limits the amount of energy that can be delivered
to the load under fault. During the start-up time, frequency
foldback is also active to limit the energy delivered to the
potentially large output capacitance of the load.
Synchronization
The internal oscillator of the LTM8025 can be synchronized
by applying an external 250kHz to 2MHz clock to the SYNC
pin. Do not leave this pin floating. When synchronizing
the LTM8025, select an R
T
resistor value that corresponds
to an operating frequency 20% lower than the intended
synchronization frequency (see the Frequency Selection
section).
In addition to synchronization, the SYNC pin controls Burst
Mode behavior. If the SYNC pin is driven by an external
clock, or pulled up above 0.7V, the LTM8025 will not en
-
ter Burst Mode operation, but will instead skip pulses to
maintain regulation instead.
Shorted Input Protection
Care needs to be taken in systems where the output will be
held high when the input to the LTM8025 is absent. This
may occur in batter
y charging applications or in battery
backup systems where a battery or some other supply is
diode ORed with the LTM8025’s output. If the V
IN
pin is
allowed to float and the SHDN pin is held high (either by a
logic signal or because it is tied to V
IN
), then the LTM8025’s
internal circuitry will pull its quiescent current through
its internal power switch. This is fine if your system can
tolerate a few milliamps in this state. If you ground the
RUN/SS pin, the input current will drop to essentially zero.
However, if the V
IN
pin is grounded while the output is
held high, then parasitic diodes inside the LTM8025 can
pull large currents from the output through the V
IN
pin.
Figure 2 shows a circuit that will run only when the input
voltage is present and that protects against a shorted or
reversed input.
PCB Layout
Most of the headaches associated with PCB layout have
been alleviated or even eliminated by the high level of
integration of the LTM8025. The LTM8025 is neverthe
-
less a switching power supply, and care must be taken to
minimize EMI and ensure proper operation. Even with the
high level of integration, you may fail to achieve specified
operation with a haphazard or poor layout. See Figure 3
for
a suggested layout. Ensure
that the grounding and
heatsinking are acceptable.
LTM8025
14
8025fc
For more information www.linear.com/LTM8025
BIAS
AUX
V
OUT
V
IN
GND GND
8025 F03
GND
THERMAL VIAS TO GND
R
T
R
ADJ
PGOOD
C
IN
C
OUT
SYNC
SHDN
applicaTions inForMaTion
Figure 2. The Input Diode Prevents a Shorted Input from
Discharging a Backup Battery Tied to the Output. It Also Protects
the Circuit from a Reversed Input. The LTM8025 Runs Only When
the Input is Present.
1. Place the R
ADJ
and R
T
resistors as close as possible to
their respective pins.
2. Place the C
IN
capacitor as close as possible to the V
IN
and GND connection of the LTM8025.
3. Place the C
OUT
capacitor as close as possible to the
V
OUT
and GND connection of the LTM8025.
4. Place the C
IN
and C
OUT
capacitors such that their
ground current flow directly adjacent or underneath
the LTM8025.
5. Connect all of the GND connections to as large a copper
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external
components and the LTM8025.
6. For good heatsinking, use vias to connect the GND cop
-
per area to the board’s internal ground planes. Liberally
distribute these GND vias to provide both a good ground
connection and thermal path to the internal planes of the
printed circuit board. Pay attention to the location and
density of the thermal vias in Figure 3. The LTM8025
can benefit from the heat-sinking afforded by vias that
connect to internal GND planes at these locations, due to
their proximity to internal power handling components.
The optimum number of thermal vias depends upon
the printed circuit board design. For example, a board
might use very small via holes. It should employ more
thermal vias than a board that uses larger holes.
Figure 3. Layout Showing Suggested External Components, GND
Plane and Thermal Vias.
Hot-Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of LTM8025. However, these capacitors
can cause problems if the LTM8025 is plugged into a live
supply (see Linear Technology Application Note 88 for
a complete discussion). The low loss ceramic capacitor
combined with stray inductance in series with the power
source forms an underdamped tank circuit, and the volt
-
age at the V
IN
pin of the LTM8025 can ring to more than
twice the nominal input voltage, possibly exceeding the
LTM8025’s rating and damaging the part. If the input
supply is poorly controlled or the user will be plugging
the LTM8025 into an energized supply, the input network
should be designed to prevent this overshoot. This can be
accomplished by installing a small resistor in series to V
IN
,
but the most popular method of controlling input voltage
overshoot is to add an electrolytic bulk capacitor to the
V
IN
net. This capacitor’s relatively high equivalent series
resistance damps the circuit and eliminates the voltage
overshoot. The extra capacitor improves low frequency
ripple filtering and can slightly improve the efficiency of
the circuit, though it is likely to be the largest component
in the circuit.
V
IN
RUN/SS
RT ADJ
V
OUT
GND
8025 F02
LTM8025
V
IN
V
OUT
AUX
BIAS
SYNC
LTM8025
15
8025fc
For more information www.linear.com/LTM8025
applicaTions inForMaTion
Thermal Considerations
The LTM8025 output current may need to be derated if it
is required to operate in a high ambient temperature or
deliver a large amount of continuous power. The amount
of current derating is dependent upon the input voltage,
output power and ambient temperature. The temperature
rise curves given in the Typical Performance Character
-
istics section can be used as a guide. These curves were
generated by a LTM8025 mounted to a 58cm
2
4-layer FR4
printed circuit board. Boards of other sizes and layer count
can exhibit different thermal behavior, so it is incumbent
upon the user to verify proper operation over the intended
system’s line, load and environmental operating conditions.
The junction to air and junction to board thermal resis
-
tances given in the Pin Configuration diagram may also
be used to estimate the LTM8025 internal temperature.
These thermal coefficients are determined for maximum
output power per JESD 51-9 “JEDEC Standard, Test Boards
for Area Array Surface Mount Package Thermal Measure
-
ments” through analysis and physical correlation. Bear in
mind that the actual thermal resistance of the L
TM8025
to
the printed circuit board depends upon the design of
the circuit board.
The die temperature of the LTM8025 must be lower than
the maximum rating of 125°C, so care should be taken in
the layout of the circuit to ensure good heat sinking of the
LTM8025. The bulk of the heat flow out of the LTM8025
is through the bottom of the module and the LGA pads
into the printed circuit board. Consequently a poor printed
circuit board design can cause excessive heating, result
-
ing in impaired performance or reliability. Please refer to
the PCB Layout section for printed circuit board design
suggestions.
The LTM8025 is equipped with a thermal shutdown that
will inhibit power switching at high junction temperatures.
The activation threshold of this function, however, is above
125°C to avoid interfering with normal operation. Thus,
it follows that prolonged or repetitive operation under a
condition in which the thermal shutdown activates neces
-
sarily means that the internal components are subjected
to temperatures above the 125°C rating for prolonged
or repetitive intervals, which may damage or impair the
reliability of the device.
Finally, be aware that at high ambient temperatures the
internal Schottky diode will have significant leakage current
increasing the quiescent current of the LTM8025.
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LTM8025IV#PBF

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Buy LTM8025IV#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 36V, 3A Buck Module Conv
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