LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
83940D DATA SHEET
2 REVISION B 3/25/15
TABLE 1. PIN DESCRIPTIONS
Number Name Type Description
1, 2, 12, 17, 25 GND Power Power supply ground.
3 LVCMOS_CLK Input Pulldown Clock input. LVCMOS / LVTTL interface levels.
4 CLK_SEL Input Pulldown
Clock select input. Selects LVCMOS / LVTTL clock
input when HIGH. Selects PCLK, nPCLK inputs when
LOW. LVCMOS / LVTTL interface levels.
5 PCLK Input Pulldown Non-inverting differential LVPECL clock input.
6 nPCLK Input
Pullup/
Pulldown
Inverting differential LVPECL clock input.
V
DD
/2 default when left fl oating.
7, 21 V
DD
Power Core supply pins.
8, 16, 29 V
DDO
Power Output supply pins.
9, 10, 11, 13, 14,
15, 18, 19, 20, 22,
23, 24, 26, 27, 28,
30, 31, 32
Q17, Q16, Q15, Q14, Q13,
Q12, Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4, Q3,
Q2, Q1, Q0
Output Clock outputs. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
C
PD
Power Dissipation Capacitance
(per output)
6pF
R
PULLup
Input Pullup Resistor 51
KΩ
R
PULLDOWN
Input Pulldown Resistor 51
KΩ
R
OUT
Output Impedance 18 28
Ω
TABLE 3A. CLOCK SELECT FUNCTION TABLE
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Control Input Clock
CLK_SEL PCLK, nPCLK LVCMOS_CLK
0 Selected De-selected
1 De-selected Selected
Inputs Outputs
Input to Output Mode Polarity
CLK_SEL LVCMOS_CLK PCLK nPCLK Q0:Q17
0 — 0 1 LOW Differential to Single Ended Non Inverting
0 — 1 0 HIGH Differential to Single Ended Non Inverting
0— 0
Biased;
NOTE 1
LOW Single Ended to Single Ended Non Inverting
0— 1
Biased;
NOTE 1
HIGH Single Ended to Single Ended Non Inverting
0 — Biased; NOTE 1 0 HIGH Single Ended to Single Ended Inverting
0 — Biased; NOTE 1 1 LOW Single Ended to Single Ended Inverting
1 0 — — LOW Single Ended to Single Ended Non Inverting
1 1 — — HIGH Single Ended to Single Ended Non Inverting
NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”.
