REVISION B 3/25/15
83940D DATA SHEET
5 LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
TABLE 4B. DC CHARACTERISTICS, V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, TA = 0° TO 70°
TABLE 5B. AC CHARACTERISTICS, V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, TA = 0° TO 70°
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage LVCMOS_CLK 2.4 V
DD
V
V
IL
Input Low Voltage LVCMOS_CLK 0.8 V
V
PP
Peak-to-Peak Input Voltage PCLK, nPCLK 300 1000 mV
V
CMR
Input Common Mode Voltage;
NOTE 1, 2
PCLK, nPCLK V
DD
- 1.4 V
DD
- 0.6 V
I
IN
Input Current ±200 µA
V
OH
Output High Voltage I
OH
= -20mA 1.8 V
V
OL
Output Low Voltage I
OL
= 20mA 0.5 V
I
DD
Core Supply Current 25 mA
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is
V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defi ned as
V
IH
.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
t
pLH
Propagation Delay
PCLK, nPCLK;
NOTE 1, 5
f ≤ 150MHz
1.7 3.2 ns
LVCMOS_CLK;
NOTE 2, 5
f ≤ 150MHz
1.7 3.0 ns
t
pLH
Propagation Delay
PCLK, nPCLK;
NOTE 1, 5
f > 150MHz 1.6 3.4 ns
LVCMOS_CLK;
NOTE 2, 5
f > 150MHz 1.8 3.3 ns
tsk(o)
Output Skew;
NOTE 3, 5
PCLK, nPCLK
Measured on
rising edge @V
DDO
/2
150 ps
LVCMOS_CLK 150 ps
tsk(pp)
Part-to-Part Skew;
NOTE 6
PCLK, nPCLK
f ≤ 150MHz
1.5 ns
LVCMOS_CLK
f ≤ 150MHz
1.3 ns
tsk(pp)
Part-to-Part Skew;
NOTE 6
PCLK, nPCLK f > 150MHz 1.8 ns
LVCMOS_CLK f > 150MHz 1.5 ns
tsk(pp)
Part-to-Part Skew;
NOTE 4, 5
PCLK, nPCLK
Measured on
rising edge @V
DDO
/2
850 ps
LVCMOS_CLK 750 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 7
0.03 ps
t
R
/ t
F
Output Rise/Fall Time 0.5 to 1.8V 0.3 1.2 ns
odc Output Duty Cycle f < 134MHz 45 50 55 %
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output V
DDO
/2.
NOTE 2: Measured from V
DD
/2 to V
DDO
/2.
NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 4: Defi ned as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 6: Defi ned as skew between outputs on different devices, across temperature and voltage ranges, and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 7: Driving only one input clock.
