6
FN6230.4
August 13, 2015
Application Information
The ISL55141, ISL55142, ISL55143 provide 1, 2 and 4 dual
threshold, three-state window comparator(s) in TSSOP or
QFN footprints. They offer a combination of speed (10ns Tpd
and wide voltage range (18V). This product directly
addresses the need for unique common-mode
characteristics while supplying a power-down feature.
Figures 4 and 5 show the stimulus setup and measurement
points for an example propagation delay measurement.
Typical room temperature results are displayed in Figure 12.
Figure 5 shows a V
INP
range of 50mV. In Figure 12 the
offset is increased in the horizontal axis from 50mV above
and below the reference (1.5V) up to 2.5V above and below
the 1.5V reference.
Two lines are displayed in Figure 12. One represents the
rising-to-rising delay (t
PDLH
)
and the other the
falling-to-falling delay (t
PDHL
).
Comparator Features
These three-state window comparators feature high output
current capability, and user defined high and low output levels
to interface with a wide variety of logic families. Each receiver
comprises two comparators and each comparator has an
independent threshold level input, making it easy to
implement (Minimum1-V
IH
)/(Maximum 0-V
IL
) logic level
comparator functions. The CV
AX
and CV
BX
pins set the
threshold levels of the A and B comparators respectively. V
OH
and V
OL
set all the comparator output levels, and V
OH
must
be more positive than V
OL
. These two inputs are unbuffered
supply pins, so the sources driving these pins must provide
adequate current for the expected load. V
OH
and V
OL
typically connect to the power supplies of the logic device
driven by the comparator outputs.
The truth table for the receivers is given in Table 1. Receiver
outputs are not tri-statable, and do not incorporate any on-chip
short circuit current protection. Momentary short circuits to
GND, or any supply voltage, will not cause permanent
damage, but care must be taken to avoid longer duration short
circuits. If tolerable to the application, current limiting resistors
can be inserted in series with the Q
AX
and Q
BX
outputs to
protect the receiver outputs from damage due to overcurrent
conditions.
Power-down Features
The ISL55141, ISL55142, ISL55143 PD pin provides a
means of reducing current consumption when the device is
not in use. Supply currents fall from ~7mA to less than 10µA
in the power-down mode. The device requires approximately
10µs to power-down and 15µs to power-up.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, good printed circuit
board layout is necessary for optimum performance. Ground
plane construction is highly recommended, lead lengths
should be as short as possible, and the power supply pins
must be well bypassed to reduce the risk of oscillation. For
normal single supply operation, where the V
EE
pin is
connected to ground, one 0.1µF ceramic capacitor should be
placed from the V
CC
pin to ground. A 4.7µF tantalum
capacitor should then be connected from the V
CC
pin to
ground. This same capacitor combination should be placed
at each supply pin to ground if split supplies are to be used.
Power Dissipation Considerations
Specifying continuous data rates, driver loads and driver
level amplitudes are key in determining power supply
requirements as well as dissipation/cooling necessities.
Driver output patterns also impact these needs. The faster
the pin activity, the greater the need to supply current and
remove heat.
FIGURE 4. t
PD
RECEIVER SWITCHING TEST CIRCUIT
FIGURE 5.
t
PD
RECEIVER PROPAGATION DELAY
MEASUREMENT POINTS
Test Circuits and Waveforms (Continued)
+
-
+
-
V
INP
Q
A
Q
B
+11 V
CC
-3 V
EE
CV
A
1.5V
CV
B
1.5V
+5V-V
OH
V
OL
Q
X
50mV
-50mV
t
PDLH
V
OH
(5V)
V
OL
(0V)
50% 50%
t
PDHL
V
INP
1.5V
1.5V
CV
A
= CV
B
= 1.5V
ISL55141, ISL55142, ISL55143
